FPGA and Linux build environment for Parallella

A forum for documenting the Parallella and Epiphany . (Not Q&A!)

Re: FPGA and Linux build environment for Parallella

Postby thai_kien » Mon Nov 21, 2016 3:50 pm

Hi,

I'm a new Parallella player. I had your project from Github > Opened in Vivado > Manually import constrains and sources into (The files were in project folder but not showed up on Vivado) > I hit Run behavior Sim and I had this problem:

ERROR: [VRFC 10-2063] Module <elink2_top> not found while processing module instance <elink2_top_i> [C:/Users/Kien/Desktop/parallella-fpga-abc1d5671a7cd59e706661a582075c0815de5ee7/7010_hdmi/7010_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v:180]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

Here is my project structure: https://www.mediafire.com/?ed44m8dj2hzdtqn

I'm not sure what went wrong. Would you help me with this please? Thank you for your time.

Best
Kien
thai_kien
 
Posts: 1
Joined: Mon Nov 21, 2016 3:36 pm

Re: FPGA and Linux build environment for Parallella

Postby peteasa » Tue Nov 22, 2016 3:16 pm

Hi Kien,

From the look of your output you are using windows. I have only used ubuntu to build the fpga. My user guide is at https://github.com/peteasa/parallella/w ... -7020_hdmi. The makefile has a few simple steps that you can run by hand.. First build the AdiHDLLib (https://github.com/peteasa/parallella-f ... akefile#L7). This creates the Analog Devices HDL libraries that are needed... you might try that first (https://github.com/peteasa/parallella-f ... /AdiHDLLib).

Once the Adi libraries are available the top level make file builds the oh source (https://github.com/peteasa/parallella-f ... akefile#L9). Actually building the oh source is independent of building the Analog Devices HDL libraries so you could try building the oh libraries separately.

Once both the Adi libraries and the oh libraries are available the fpga should be relatively easily built. I am using a tcl script that tells vivado where to find the libraries (set_property "ip_repo_paths" https://github.com/peteasa/parallella-f ... mi.tcl#L54). If you try to load the xpr project file before the libraries have been built then nothing will work for you!

Now you know the basic steps that are needed, have a go in the windows environment running the top level make file and see if that helps you. If not you will have to build each library separately or perhaps create a virtual machine and load the linux version of Vivado!!

Hope this helps.

Peter.
User avatar
peteasa
 
Posts: 114
Joined: Fri Nov 21, 2014 7:04 pm

Re: FPGA and Linux build environment for Parallella

Postby promach » Mon Dec 12, 2016 9:09 am

[promach@localhost parallella-fpga]$ make
make -C AdiHDLLib/ lib
make[1]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib'
make -C library/ all
make[2]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library'
make -C axi_clkgen
make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_clkgen'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1
make[3]: *** [Makefile:44: axi_clkgen.xpr] Error 127
make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_clkgen'
make[2]: [Makefile:96: lib] Error 2 (ignored)
make -C axi_hdmi_tx
make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_hdmi_tx_ip.tcl >> axi_hdmi_tx_ip.log 2>&1
make[3]: *** [Makefile:56: axi_hdmi_tx.xpr] Error 127
make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
make[2]: [Makefile:97: lib] Error 2 (ignored)
make -C axi_spdif_tx
make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_spdif_tx_ip.tcl >> axi_spdif_tx_ip.log 2>&1
make[3]: *** [Makefile:46: axi_spdif_tx.xpr] Error 127
make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
make[2]: [Makefile:98: lib] Error 2 (ignored)
make[2]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library'
make[1]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib'
make -C oh/src/parallella/fpga/parallella_base all
make[1]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'
vivado -mode batch -source run.tcl
make[1]: vivado: Command not found
make[1]: *** [Makefile:18: all] Error 127
make[1]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'
make: *** [Makefile:8: all] Error 2


or

http://paste2.org/z5JI4BAx

I am having make problem at https://github.com/peteasa/parallella-fpga/blob/abc1d5671a7cd59e706661a582075c0815de5ee7/AdiHDLLib/library/axi_clkgen/Makefile#L44
manually running line 44 in terminal gives me no error....

Any idea ? Am I missing anything ?
promach
 
Posts: 5
Joined: Mon Dec 12, 2016 9:03 am

Re: FPGA and Linux build environment for Parallella

Postby peteasa » Mon Dec 12, 2016 10:21 am

Hi promach,

Thanks for having a go with the FPGA build.. The following seems quite important - vivado: Command not found -

I have a user guide that you might like to try and follow at https://github.com/peteasa/parallella/w ... ng-started. In particular look at the section "Installing required software for Xilinx fpga development". Once installed follow the guide at https://github.com/peteasa/parallella/w ... -7020_hdmi.

Hope this helps

Peter.
User avatar
peteasa
 
Posts: 114
Joined: Fri Nov 21, 2014 7:04 pm

Re: FPGA and Linux build environment for Parallella

Postby promach » Tue Dec 13, 2016 12:22 am

Manually running "vivado -mode batch -source run.tcl" gives me no error.


Am I missing something else ?

I am using Vivado 2016.2
I do not think enviroment variable "ADI_IGNORE_VERSION_CHECK" in https://wiki.analog.com/resources/fpga/docs/releases is relevant, but let me try.

I am still having error http://paste2.org/YV8nIfxP , but the error "vivado command not found" is gone after I have followed https://github.com/peteasa/parallella/wiki/Building-7020_hdmi

I am going to try https://parallella.org/forums/viewtopic.php?f=10&t=3446

[promach@localhost parallella-fpga]$ make
make -C AdiHDLLib/ lib
make[1]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib'
make -C library/ all
make[2]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library'
make -C axi_clkgen
make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_clkgen'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1
make[3]: *** [Makefile:44: axi_clkgen.xpr] Error 1
make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_clkgen'
make[2]: [Makefile:96: lib] Error 2 (ignored)
make -C axi_hdmi_tx
make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_hdmi_tx_ip.tcl >> axi_hdmi_tx_ip.log 2>&1
make[3]: *** [Makefile:56: axi_hdmi_tx.xpr] Error 1
make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_hdmi_tx'
make[2]: [Makefile:97: lib] Error 2 (ignored)
make -C axi_spdif_tx
make[3]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui .Xil
vivado -mode batch -source axi_spdif_tx_ip.tcl >> axi_spdif_tx_ip.log 2>&1
make[3]: *** [Makefile:46: axi_spdif_tx.xpr] Error 1
make[3]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library/axi_spdif_tx'
make[2]: [Makefile:98: lib] Error 2 (ignored)
make[2]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib/library'
make[1]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/AdiHDLLib'
make -C oh/src/parallella/fpga/parallella_base all
make[1]: Entering directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'
vivado -mode batch -source run.tcl

****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source run.tcl
# source ./system_params.tcl
## set design parallella_base
## set projdir ./
## set root "../../.."
## set partname "xc7z020clg400-1"
## set hdl_files [list \
## $root/parallella/hdl \
## $root/common/hdl/ \
## $root/emesh/hdl \
## $root/emmu/hdl \
## $root/axi/hdl \
## $root/emailbox/hdl \
## $root/edma/hdl \
## $root/elink/hdl \
## ]
## set ip_files [list \
## $root/xilibs/ip/fifo_async_104x32.xci \
## ]
## set constraints_files []
# source ../../../common/fpga/create_ip.tcl
## create_project -force $design $projdir -part $partname
## set_property target_language Verilog [current_project]
## set_property source_mgmt_mode None [current_project]
## if {[string equal [get_filesets -quiet sources_1] ""]} {
## create_fileset -srcset sources_1
## }
## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files
## set_property top $design [get_filesets sources_1]
## if {[string equal [get_filesets -quiet constraints_1] ""]} {
## create_fileset -constrset constraints_1
## }
## if {[llength $constraints_files] != 0} {
## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files
## }
## if {[llength $ip_files] != 0} {
##
## #Add to fileset
## add_files -norecurse -fileset [get_filesets sources_1] $ip_files
##
## #Set mode for IP
## foreach file $ip_files {
## #TODO: is this needed?
## set file_obj [get_files -of_objects [get_filesets sources_1] $file]
## set_property "synth_checkpoint_mode" "Singular" $file_obj
## }
## #RERUN/UPGRADE IP
## upgrade_ip [get_ips]
## }
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.2/data/ip'.
WARNING: [IP_Flow 19-2162] IP 'fifo_async_104x32' is locked:
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_async_104x32' has a newer major version in the IP Catalog.
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_async_104x32' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
ERROR: [Common 17-107] Cannot change read-only property 'synth_checkpoint_mode'.
Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.

while executing
"source ../../../common/fpga/create_ip.tcl"
(file "run.tcl" line 4)
INFO: [Common 17-206] Exiting Vivado at Tue Dec 13 08:53:26 2016...
make[1]: *** [Makefile:18: all] Error 1
make[1]: Leaving directory '/home/promach/Documents/Grive/Personal/Digital/Parallella/parallella/parallella-fpga/oh/src/parallella/fpga/parallella_base'
make: *** [Makefile:8: all] Error 2
promach
 
Posts: 5
Joined: Mon Dec 12, 2016 9:03 am

Re: FPGA and Linux build environment for Parallella

Postby peteasa » Tue Dec 13, 2016 9:33 am

Hi promach,

Now things get a bit more interesting... Moving to a new version of vivado is not necessarily easy. Xilinx seem to change the tcl interface quite frequently. As a result ADI only use every other version of vivado because it takes them time to catch up with scripting changes. I see from https://github.com/analogdevicesinc/hdl/releases that they now support 2016.2 so you will be good to go. You would need to update the contents of parallella/parallella-fpga/AdiHDLLib. I try to take only the things that are needed. Last time this was axi_clkgen, axi_hdmi_tx, axi_spdif_tx.. the project (adv7511/zc702) is taken but I speed up the build by not including it when I release. library/common and library/interfaces and library/prcfg and library/scripts are shared (except I dont need any altera bits). If you do a diff between the latest ADI release and my snapshot you will see the changes. Once that is working you will also likely need to update the tcl scripts for oh... https://github.com/parallella/oh/blob/m ... bd.tcl#L13 sets the script version to 2015.2 and complains if you are not using 2015.2..

Looking at the changes that ADI have made will give you a clue as to what to change in the oh tcl scripts.

Dont forget two things:

    1. I have prebuilt an fpga bit bin so you could use that if you did not want to make changes to the fpga
    2. If you are building the fpga then you can have multiple versions of vivado on your system at the same time so you could build with 2015.2 then update the project created

Assuming that you plan to stick with 2016.2 then if you do make progress you could provide a contribution to oh and to parallella-fpga with the changes that you make to get it all to work... I am in the middle of something else at the moment so it will be a bit of time before I can make progress with fixing this.

Peter.
User avatar
peteasa
 
Posts: 114
Joined: Fri Nov 21, 2014 7:04 pm

Previous

Return to Quick Start Guides , Documentation, Examples (Start Here!)

Who is online

Users browsing this forum: No registered users and 3 guests

cron