Isn't there any board file for Parallella to use in Vivado?

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Isn't there any board file for Parallella to use in Vivado?

Postby parallella-project » Fri May 19, 2017 2:01 pm

Is there any board file for parallella (like zedboard, zybo or ...) to use for configuration of Vivado at the start of creating a project (when choosing the development board)?
I mean add Parallella board to this dialogue:
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Re: Isn't there any board file for Parallella to use in Viva

Postby svartalf » Fri Jun 23, 2017 4:09 pm

That's just an FPGA chip chooser. Pick one of the "boards" and adjust accordingly. Main reason I can think of for it not having a "board" file is because they're not Digilent or Avnet. Xilinx works with them quite tightly- and none of this gets into the reality that you're not going to have a "board" file for a design you make in the first place. You're going to pick a rough board or the FPGA chip you know is on your device. You're not going to get a board file for anything other than an Arty on Artix setups, for example...
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Re: Isn't there any board file for Parallella to use in Viva

Postby adexmont » Sun Aug 06, 2017 1:12 pm

not sure this is what you r looking for but may be one of the way :
I cloned parallella-fpga github repository and installed vivado 2017.2 web (free) version.
I opened a new project in the cloned folder and retrieving the parallella source from there.

Vivado looks like simulate quite well all the steps (not able to say if any of that warning may be critical)

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(13) - Only lower order bits will be connected.

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(13) - Only lower order bits will be connected.

WARNING: [Runs 36-53] Possible issues detected after target generation. Generation state is unexpected for target 'Simulation'. Expected 'Generated', got 'Stale' for source '/home/user /parallella/parallella-fpga/adexparallella/adexparallella.srcs/sources_1/bd/base_zynq/base_zynq.bd'

This was the 3 ones marked in red that may provide some hint for some critical issues.

I ask here but please reply in post https://parallella.org/forums/viewtopic.php?f=51&t=4145 Can anyone point me in whitch part the "gpu/bitstraem" already in use is described/implemented ?

Thanks
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Re: Isn't there any board file for Parallella to use in Viva

Postby frankbuss » Tue Aug 08, 2017 6:39 am

adexmont wrote:not sure this is what you r looking for but may be one of the way :
I cloned parallella-fpga github repository and installed vivado 2017.2 web (free) version.
I opened a new project in the cloned folder and retrieving the parallella source from there.

Vivado looks like simulate quite well all the steps (not able to say if any of that warning may be critical)


And does it work? I looked at the parallella-hw repository, but it says "All Parallella related FPGA sources have been moved to the OH! library library and released under MIT license.". So I tried this and the scripts in the "oh" repository, but they failed with Vivado 2017.2.

In which folder exactly opened you a new project and how did you include the source? Last time I tried FPGA development with Parallella was some years ago and then I think I used Xilinx ISE and PlanAhead. Could you upload a zip file of the Vivado project somewhere?

Looks like "parallella-fpga" has more recent commits than "oh"? Really confusing to determine which repository I should use. Which one was used for the last official Parabuntu release?
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Re: Isn't there any board file for Parallella to use in Viva

Postby adexmont » Tue Aug 08, 2017 8:47 am

And does it work?
... my optimism say to not ... btw i'm just random clicking and try to get autosetup working... i'm not able to understand what i'm doing.

I'm on a 7020 so i gave the basic folder as parallella-fpga/???7020??? but looks like the only component vivado find by itself is the elink the rest of the board is not imported.

Tryed to use the function to connect vivado through vivado hardware server (tryed to install on parallella but java return error that may thinking about a wrong architecture) so not able to install.

I'm just playing with vivado on random folder but as you said before it's hard to understand what folder should be used to retrieve the whole design base (more difficult if you r not able to understand the documentation :P ) maybe by comparing datasheet I/O to verilog code you can understand what component do what but it's a long way and may be not scientific but empiric.
Thanks for any suggestion on how to approach this way of communication between human and board.

PS
In The mean while that someone who is able to provide a stable and everyday usable system i'm just trying to use this device for what i think i can be usefull but i'm not getting toomuch result, just learning something but understanding my lack are very big to deal with this board ... i have some spare time and a big will to play with this board... but maybe need some training or some small task to begin and learn... so please feel pfree to contact me to set up a voluntary work team for noob task (keep ubuntu updated with all it's pkgs for example... teach me how and i'll do it ... maybe)

Thanks again
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Re: Isn't there any board file for Parallella to use in Viva

Postby olajep » Wed Aug 09, 2017 2:48 pm

frankbuss wrote:Looks like "parallella-fpga" has more recent commits than "oh"? Really confusing to determine which repository I should use. Which one was used for the last official Parabuntu release?

I used parallella-fpga to create bitstreams for the Parabuntu 2016.11 HDMI images.
HT to Peter @peteasa!
Upstream at https://github.com/peteasa/parallella-fpga

Prerequisites:
Vivado 2015.4 and SDK 2015.4 (needed to change from 2015.2 since the ADI IPs required vivado 2015.4)

Code: Select all
source /opt/Xilinx/Vivado/2015.4/settings64.sh
source /opt/Xilinx/SDK/2015.4/settings64.sh
git clone --recursive https://github.com/parallella/parallella-fpga.git
cd parallella-fpga
make


// Ola
_start = 266470723;
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Re: Isn't there any board file for Parallella to use in Viva

Postby frankbuss » Sat Aug 12, 2017 3:46 am

olajep wrote:
frankbuss wrote:
Code: Select all
source /opt/Xilinx/Vivado/2015.4/settings64.sh
source /opt/Xilinx/SDK/2015.4/settings64.sh
git clone --recursive https://github.com/parallella/parallella-fpga.git
cd parallella-fpga
make



So for the HDMI version you use a different repository, a different Vivado version, and a different github repository than for the headless version (as you wrote in this thread the repository at https://github.com/parallella/oh ) ? This doesn't sound right :?
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Re: Isn't there any board file for Parallella to use in Viva

Postby frankbuss » Wed Aug 16, 2017 10:43 pm

I ported the accelerator to Vivado 2017.2. Looks like this version is a bit more picky about missing wires etc., needed some fixed in OH components. These are the differences:

https://github.com/FrankBuss/oh/commit/ ... 807ceceefb

The system_bd.tcl file was just re-created by Vivado as suggested from the script, with "write_bd_tcl" on the Tcl command line. I guess it would be as easy with the parallella project.

BTW, I noticed the OH components are very unfinished, like there is a lot of empty modules and skeleton code. Is this project still alive and do people write code for it? Personally I don't like Verilog, I prefer VHDL. But recently I discovered Chisel ( https://chisel.eecs.berkeley.edu ), which makes it much easier to write HDL programs, because it has the power of Scala as the backend. For example exhaustive testbenches are much simpler to write and run. Or need a ROM with a sin-table? No problem with a real language like Scala, just one line to generate it inline for the synthesizing step. This might be a better base for the OH framework.
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