So, the LEON3 CPU is a soft-core which you can instantiate on the FPGA portion of the Zynq chip. In this regard, using the Parallella or any other board containing the Zynq chip is the same. You can find the .xdc file on the Parallella github (.ucf is specific to ISE and you need to program Zynq with Vivado).
The Epiphany is another chip that is connected to the Zynq chip. For this connection to be possible, the FPGA portion of the Zynq implements some glue logic that enables communication between the Zynq ARM cores and the Epiphany cores.
The easy way to implement the Leon3 CPU in the FPGA is to implement it just in like any other Zynq, by creating a new FPGA bitstream. The disadvantage is that you will not have the logic necessary to communicate between Zynq ARM cores and Epiphany cores. In this way, you can have Epiphany or the Leon3 CPU, but not both at the same time.
The non-easy way is to combine the Leon3 CPU with the glue logic required for communication between Zynq ARM cores and Epiphany cores. You would have to develop you own communication between Epiphany cores and Leon3 CPU.
I hope this helps
by bgeorge » Tue Apr 18, 2017 12:33 pm