by Frida » Fri Aug 22, 2014 6:52 pm
Well it has been a while since.
Is there anybody here, that have looked at the logik from the FPGA to the USB.??
Is the "STP" "p0_usb_stp" signal high, until the FPGA has sat up the data lines to the USB, and is ready to talk to the USB.??
I found out, I have a window from ca. 30 ms. to 10sec., where I can held down "BOARD_RESET_L", and still have my USB to work.
When login is reached, I can held "BOARD_RESET_L" low for a minute or so, and when I release it , it all works again.
I hope that somebody with insight in the FPGA will chime in.