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Parallella Community • View topic - Creating an FPGA accelerator in 15 minutes

Creating an FPGA accelerator in 15 minutes

A forum for documenting the Parallella and Epiphany . (Not Q&A!)

Creating an FPGA accelerator in 15 minutes

Postby aolofsson » Thu Jan 21, 2016 8:50 pm

I finally got around to creating an FPGA "sandbox" example for parallella.

Completely scripted. As long as you have Vivado installed, just edit the verilog code and build with one command. No dependency on Xilinx proprietary IP generator. No need to open the GUI.

https://www.parallella.org/2016/01/21/c ... 5-minutes/
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Re: Creating an FPGA accelerator in 15 minutes

Postby theover » Mon Jan 25, 2016 11:02 pm

I've downloaded the git project, ran the supplied commands after correcting the first "cd" command, and after a minute or so, there were errors in the build. Also, I understand this project makes use of the constructs usually used for the Epiphany chip, but is there an example how to address the resulting accelerator from C/Linux, and if so, is that instead of the Epiphany or, in addition to ?

T.V.
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Re: Creating an FPGA accelerator in 15 minutes

Postby aolofsson » Mon Jan 25, 2016 11:19 pm

-please report error here or file an issue?

-the software is linux. If youwant to runin user space with /dev/mem you will need to run as sudo.
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Re: Creating an FPGA accelerator in 15 minutes

Postby Melkhior » Sun Aug 28, 2016 10:38 am

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Re: Creating an FPGA accelerator in 15 minutes

Postby peteasa » Wed Aug 31, 2016 6:43 am

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Re: Creating an FPGA accelerator in 15 minutes

Postby Melkhior » Wed Aug 31, 2016 12:47 pm

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Re: Creating an FPGA accelerator in 15 minutes

Postby cpantel » Thu Sep 06, 2018 1:07 am

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Re: Creating an FPGA accelerator in 15 minutes

Postby olajep » Thu Sep 27, 2018 2:00 am

_start = 266470723;
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Re: Creating an FPGA accelerator in 15 minutes

Postby cpantel » Mon Oct 08, 2018 1:45 am

Hi

About the branch:

If I checkout "stable", the landscape changes far beyond my little current knowledge.

Anyway, I will try this way, in a few days (weeks?) I'll tell you.


About the versions:

~/Xilinx/Vivado/2015.2/bin/vivado -version
Vivado v2015.2 (64-bit)
SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.


./Xilinx/Vivado/2015.4/bin/vivado -version
Vivado v2015.4 (64-bit)
SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015

thank you
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Re: Creating an FPGA accelerator in 15 minutes

Postby cpantel » Thu Oct 18, 2018 10:11 pm

Hello,

Finally, I closed my eyes and zen picked a commit near master that just worked (258cda9). Then, kind of bisected (70a6f14,2f91330, fbfe559, afccd4a, ee2e234) towards master until the the last working commit (afccd4a).




It seem ok till now.

1) First question:

when I tried the xdevcfg method, it seems to timeout

cat parallella.bit.bin > /dev/xdevcfg
cdns-i2c e0004000.i2c: timeout waiting on completion
cdns-i2c e0004000.i2c: timeout waiting on completion
cdns-i2c e0004000.i2c: timeout waiting on completion
...

it is normal? I left it two minutes, I do not think so.


2) I burned the bitstream in the BOOT partition, compiled driver.c and test.c ok, but when run, it fails:

f_map: No such file or directory
Segmentation fault

when tries to open /dev/epiphany, that does not exist.

[driver.c]
//Open /dev/mem file if not already
if(mem_fd < 1) {
mem_fd = open ("/dev/epiphany", O_RDWR);
if (mem_fd < 1) {
perror("f_map");
return -1;
}
}


I saw viewtopic.php?f=48&t=1528, but it seems to old (2014), it should've failed with the 15 minutes example (2016-2017)

My uname -a:

Linux parallella 4.6.0+ #1 SMP PREEMPT Wed Dec 7 13:27:40 CET 2016 armv7l armv7l armv7l GNU/Linux

Any hints or advice?
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