Audio playback

[theover]

I didn't know TI had power OpAmps like that. Bit of a waste to put all that energy into heat to reduce voltage for a high efficiency digital poweramp, but seems like a fun project.

I'm looking at making my porcupine pins drive all kinds of digital audio controls from C using Vivado_hls, that should make things a lot easier! Quality digital volume controls, existing and self-made DACs, audio synthesis blocks with simple outputs like square wave oscillators without a fixed sample frequency, communicating over MIDI, wireless control via a simple Android App, lots and lots of possibilities still.

T.

[patc]

I plan to use buck converters for my other project (Parallella + 4 homemade digital amps)
cf. picture below: buck converter module on the right handside which I received a couple of weeks ago from China (ebay)

Regarding my current setup, so far I'm pretty happy with the OPA549 and it just gets mildly warm. The load is 8 Ohms so it's not like having to dissipate a lot of power when the output voltage is low.

AFAIC I'm pretty curious to listen compare linear vs switching PS

[patc]

image #1: Parallella sandwich with a glass of ferric chloride

image #2: measurement microphone ADC module squeezed on the side panel. The part not populated yet is the provision to connect to a 48V phantom feed supply for microphone if needed.

image #3: build of this project basically completed (IR receiver still missing though). Next on the line: measurements, calibrations and testing.

So far all the functionalities seem to be working pretty well. I'm curious to compare the 3 different channels digital amp/DSD/NOS-PCM with each other on full-range speakers, then go tri-amp.

[patc]

I wasn't happy with the sigma-delta modulator output level when I did the calibration to align the amps level together. It's using only 18-bit out of the 20 feeding it and I decided to give a shot to a new digital amp IC, the SSM-3582 from Analog Devices: 2 x 15W and the sigma-delta modulator is integrated with the class-D amp in the same chip, and so far I like it.

Added the IR receiver. The driver is wrapped into a master AXI stream linked to an AXI stream FIFO which generates an interrupt to the cortex ARM everytime a key is pushed on the remote. The IR cover was scrapped from an old laptop.

Current setup fully operationnal
upsampling to 88200 - digital room correction - FIR crossovers
- low-pass 300Hz -> digital amp SSM-3582 -> Altec 515 in Onken cabinet
- band-pass 300Hz-3000Hz -> 300B tube amp -> YL-55000 compression drivers with MB-90 horns
- high-pass 3000Hz -> Denon analog amp -> Visaton MHT-12 ribbon tweeters

[patc]

Quad 2x15W digital amps

Same box but new backpanel plate and 300W SMPS instead of 120W linear power supply (actually 200W SMPS when there is no fan)

15W/channel doesn't seem much but it's more than enough in my setup. Later on I might try to beef the bass channel up to 30W or 60W to get some more extra headroom.

[patc]

A tip some may find useful

The Vivado Integrated Logic Analyzer (ILA) is an outstanding tool but can be frustrating to operate. Many times I found myself in the situation where I placed debug marks on the synthesized schematic, set up debug core and got everything working fine but then after changing the design a bit to try out something else, I could get some constraint missing errors which sometimes could be solved by disconnecting completely the debug core and doing a setup again, but some other times I had to revert to a version without debug and restart from scratch (okay, still have tons to learn about Vivado).

Eventually my Good Star kicked in as I found out a method which works great:

- add an AXI_GPIO IP to the design and set the GPIO Width to the number of desired probes (All Inputs)
- mark the GPIO as Debug and Run Connection Automation to add and set a SYSTEM_ILA IP (picture #1)
- from the HDL wrapper, pass the gpio_rtl_tri_i to the desired module to debug (picture #2)
- connect to the signals to analyze (picture #2)
- debug (picture #3)
- make changes and re-generate without having to worry any longer about mismatch hassles
- solve the problem in no time and go sip a beer!

More generally, if possible, try to isolate the problem and make the design as small as possible so that it doesn't take too much time to build.

I suppose this method is described somewhere because the Run Connection Automation is setting ILA properly.

For the story, I had 4 sources outputting with different SPDIF interfaces 24-bit @88200 to a Zynq emio set as spdif input. 3 sources were working flawlessly but I got only garbage from the fourth one. Yet when this source was connected to some other equipments, everything was perfect so it had to be something in the vhdl code. For this kind of problem it's necessary to take a close look deep down at the real time data and I find the ILA "best of the class".

[patc]

Connected the Parallella blackbox directly to eight loudspeakers, did a room measurement to generate the DRC compensation filters and have been listening to music with it for the past days.


A comment regarding the digital amps limited output power (15W/channel)
for contemporary music the average audio level is pretty high so everything is fine, but for classical music the average can be much lower resulting in a volume not always as loud as I would like it to be (when the neighbour is out)

In my setup the loudspeakers have the following sensitivity:
- bass -11dB
- low midrange 0dB (reference)
- midrange -2dB
- high -5dB

so the max volume is pretty much limited with the bass.

Now the SSM-3582 from Analog Devices can be set to a volume higher than 0dB provided the input maximum level doesn't exceed the corresponding increase in the negative scale. For example if the SSM-3582 volume is set to +3dB, the input peak should never exceed -3dB else there will be clipping.

So when the average audio level is low, it seems okay to increase the volume level up to around +6dB (high minus bass) as there is low risk for bass (20 to 300 Hz) to ever clip. And to stay on the safe side anyway, the FPGA constantly compares the samples after bass crossover with the max value set by the PS and sends an interrupt to the PS in case of peak excess so that the PS can decrease the volume level to avoid clipping.

Note that after room correction convolution done in the PS, the data is sent to the FPGA which does the crossover FIR for each channel and then sends data directly to the respective SSM-3582 using the I2S protocol. SSM-3582 settings, like volume setting, are done by the PS with the I2C protocol.

[patc]

wrap up:

[patc]

integration of a sata cdrom drive using a pata to sata adapter from Logilink (with bss-138 based level shifters)

below, my vhdl code to test feasibility. data transfer rate cd to bram = ~15Mbytes/s

Easy and low cost method but there are not enough gpios left over on the Parallella to accomodate everything.

Two and half years have passed already since I got my first Parallella and it has been incredibly fun.

Thank you