carlos@a10 ~/parallella/github/oh_2015.2/src/accelerator/fpga $ ./build.sh rm: cannot remove 'system_wrapper.bit.bin': No such file or directory rm: cannot remove 'bit2bin.bin': No such file or directory ****** Vivado v2015.4 (64-bit) **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015 **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source package.tcl # source ./ip_params.tcl ## set design axi_accelerator ## set projdir ./ ## set root "../.." ## set partname "xc7z020clg400-1" ## set hdl_files [list \ ## $root/accelerator/hdl \ ## $root/common/hdl/ \ ## $root/emesh/hdl \ ## $root/emmu/hdl \ ## $root/axi/hdl \ ## $root/emailbox/hdl \ ## $root/edma/hdl \ ## $root/elink/hdl \ ## ] ## set ip_files [] ## set constraints_files [] # source ../../common/fpga/create_ip.tcl ## create_project -force $design $projdir -part $partname ## set_property target_language Verilog [current_project] ## set_property source_mgmt_mode None [current_project] ## if {[string equal [get_filesets -quiet sources_1] ""]} { ## create_fileset -srcset sources_1 ## } ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files ## set_property top $design [get_filesets sources_1] ## if {[string equal [get_filesets -quiet constraints_1] ""]} { ## create_fileset -constrset constraints_1 ## } ## if {[llength $constraints_files] != 0} { ## add_files -norecurse -fileset [get_filesets constraints_1] $constraints_files ## } ## if {[llength $ip_files] != 0} { ## file delete -force ip_tmp ## file mkdir ip_tmp ## ## #Set mode for IP ## foreach file $ip_files { ## set file_name [file tail $file] ## set ip_name [file rootname [file tail $file]] ## set local_file ip_tmp/$file_name ## ## # Create local copy ## file copy $file ip_tmp ## add_files -norecurse -fileset [get_filesets sources_1] $local_file ## ## # Upgrade if needed ## set locked [get_property IS_LOCKED [get_ips $ip_name]] ## set upgrade [get_property UPGRADE_VERSIONS [get_ips $ip_name]] ## if {$upgrade != "" && $locked} { ## upgrade_ip [get_ips $ip_name] ## } ## ## #TODO: is this needed? ## set local_file_obj [get_files -of_objects [get_filesets sources_1] $local_file] ## set_property "synth_checkpoint_mode" "Singular" $local_file_obj ## } ## ## ## } ## ipx::package_project -import_files -force -root_dir $projdir WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux7.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_pwr_isohi.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_edgealign.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux2.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_csa42.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_stretcher.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_lat1.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_7seg_decode.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux8.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_crc32_8b.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_bin2onehot.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_pll.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_rise2pulse.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_fifo_cdc.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_oddr.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_8b10b_encode.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_fifo_generic.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_clockgate.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_abs.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_edge2pulse.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_csa92.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_shifter.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_fifo_async.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_gray2bin.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_pwr_buf.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_reg1.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux12.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_parity.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_reg0.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_csa32.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_crc.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/cfg_generic.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_ser2par.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux4.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_clockdiv.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_delay.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_clockmux.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_8b10b_decode.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_csa62.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux3.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_pwr_isolo.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux9.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_clockor.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux5.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_mux6.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_standby.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_datagate.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_par2ser.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_fall2pulse.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_lat0.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_tristate.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_edgedetect.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_iddr.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_pulse2pulse.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_add.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_buffer.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_counter.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_memory_sp.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_bitreverse.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_rsync.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_bin2gray.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_crc32_64b.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_debouncer.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/common/hdl/oh_pwr_gate.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emesh/hdl/emesh_if.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emesh/hdl/emesh_readback.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emesh/hdl/emesh_constants.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emesh/hdl/emesh_wralign.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emesh/hdl/ememory.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emesh/hdl/emesh_rdalign.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emmu/hdl/emmu.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emailbox/hdl/emailbox.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/emailbox/hdl/emailbox_regmap.vh'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/edma/hdl/edma_regs.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/edma/hdl/edma_dp.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/edma/hdl/edma_regmap.vh'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/edma/hdl/edma_ctrl.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/edma/hdl/edma.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx_protocol.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx_remap.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx_core.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_cfg.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_arbiter.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/axi_elink.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_fifo.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/elink_cfg.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_remap.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/elink.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_protocol.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_io.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx_fifo.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/etx_clocks.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/elink_regmap.vh'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx_arbiter.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/erx_cfg.v'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/elink_constants.vh'. WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: '/home/parallella/github/oh_2015.2/src/elink/hdl/ecfg_if.v'. INFO: [Common 17-14] Message 'IP_Flow 19-3833' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/carlos/Xilinx/Vivado/2015.4/data/ip'. CRITICAL WARNING: [HDL 9-870] Macro is not defined. [src/oh_memory_dp.v:36] CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_memory_dp.v:36] CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_dsync.v:18] INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/accelerator_regmap.vh" from the top-level HDL file. INFO: [IP_Flow 19-2228] Inferred bus interface "m_axi" of definition type "xilinx.com:interface:aximm:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi" of definition type "xilinx.com:interface:aximm:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "m_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "irq" of definition type "xilinx.com:signal:interrupt:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "m_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "sys_clk" of definition type "xilinx.com:signal:clock:1.0". INFO: [IP_Flow 19-818] Not transferring dependency attribute "((2 * spirit:decode(id('MODELPARAM_VALUE.AW'))) + 40)" into user parameter "PW". ## ipx::remove_memory_map {s_axi} [ipx::current_core] ## ipx::add_memory_map {s_axi} [ipx::current_core] ## ipx::associate_bus_interfaces -busif s_axi -clock sys_clk [ipx::current_core] ## ipx::associate_bus_interfaces -busif m_axi -clock sys_clk [ipx::current_core] WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead ## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]] WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead ## ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]] WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead ## set_property range {65536} [ipx::get_address_block axi_lite \ ## [ipx::get_memory_map s_axi [ipx::current_core]]] ## set_property vendor {www.parallella.org} [ipx::current_core] ## set_property library {user} [ipx::current_core] ## set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ## set_property vendor_display_name {ADAPTEVA} [ipx::current_core] ## set_property company_url {www.parallella.org} [ipx::current_core] ## set_property supported_families { \ ## {virtex7} {Production} \ ## {qvirtex7} {Production} \ ## {kintex7} {Production} \ ## {kintex7l} {Production} \ ## {qkintex7} {Production} \ ## {qkintex7l} {Production} \ ## {artix7} {Production} \ ## {artix7l} {Production} \ ## {aartix7} {Production} \ ## {qartix7} {Production} \ ## {zynq} {Production} \ ## {qzynq} {Production} \ ## {azynq} {Production} \ ## {zynquplus} {Production} \ ## } [ipx::current_core] WARNING: [IP_Flow 19-4623] Unrecognized family virtex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qvirtex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family kintex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family kintex7l. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family qkintex7l. Please verify spelling and reissue command to set the supported files. WARNING: [IP_Flow 19-4623] Unrecognized family zynquplus. Please verify spelling and reissue command to set the supported files. ## ipx::archive_core [concat $design.zip] [ipx::current_core] ## exit INFO: [Common 17-206] Exiting Vivado at Wed Sep 5 21:57:42 2018... ****** Vivado v2015.4 (64-bit) **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015 **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source run.tcl # source ./run_params.tcl ## set design system ## set projdir ./ ## set partname "xc7z020clg400-1" ## set ip_repos [list "."] ## set hdl_files [] ## set constraints_files [] # source ../../common/fpga/system_init.tcl ## create_project -force $design $projdir -part $partname ## set_property target_language Verilog [current_project] ## if {[info exists board_part]} { ## set_property board_part $board_part [current_project] ## } ## set report_dir $projdir/reports ## set results_dir $projdir/results ## if ![file exists $report_dir] {file mkdir $report_dir} ## if ![file exists $results_dir] {file mkdir $results_dir} ## set other_repos [get_property ip_repo_paths [current_project]] ## set_property ip_repo_paths "$ip_repos $other_repos" [current_project] ## update_ip_catalog INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/parallella/github/oh_2015.2/src/accelerator/fpga'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/carlos/Xilinx/Vivado/2015.4/data/ip'. ## create_bd_design "system" Wrote : ## source $projdir/system_bd.tcl ### set scripts_vivado_version 2015.4 ### set current_vivado_version [version -short] ### if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ### puts "" ### puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." ### ### return 1 ### } ### if { [get_projects -quiet] eq "" } { ### puts "ERROR: Please open or create a project!" ### return 1 ### } ### set design_name system ### set errMsg "" ### set nRet 0 ### set cur_design [current_bd_design -quiet] ### set list_cells [get_bd_cells -quiet] ### if { ${design_name} eq "" } { ### # USE CASES: ### # 1) Design_name not set ### ### set errMsg "ERROR: Please set the variable to a non-empty value." ### set nRet 1 ### ### } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { ### # USE CASES: ### # 2): Current design opened AND is empty AND names same. ### # 3): Current design opened AND is empty AND names diff; design_name NOT in project. ### # 4): Current design opened AND is empty AND names diff; design_name exists in project. ### ### if { $cur_design ne $design_name } { ### puts "INFO: Changing value of from <$design_name> to <$cur_design> since current design is empty." ### set design_name [get_property NAME $cur_design] ### } ### puts "INFO: Constructing design in IPI design <$cur_design>..." ### ### } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { ### # USE CASES: ### # 5) Current design opened AND has components AND same names. ### ### set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ### set nRet 1 ### } elseif { [get_files -quiet ${design_name}.bd] ne "" } { ### # USE CASES: ### # 6) Current opened design, has components, but diff names, design_name exists in project. ### # 7) No opened design, design_name exists in project. ### ### set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." ### set nRet 2 ### ### } else { ### # USE CASES: ### # 8) No opened design, design_name not in project. ### # 9) Current opened design, has components, but diff names, design_name not in project. ### ### puts "INFO: Currently there is no design <$design_name> in project, so creating one..." ### ### create_bd_design $design_name ### ### puts "INFO: Making design <$design_name> as current_bd_design." ### current_bd_design $design_name ### ### } INFO: Constructing design in IPI design ... ### puts "INFO: Currently the variable is equal to \"$design_name\"." INFO: Currently the variable is equal to "system". ### if { $nRet != 0 } { ### puts $errMsg ### return $nRet ### } ### proc create_root_design { parentCell } { ### ### if { $parentCell eq "" } { ### set parentCell [get_bd_cells /] ### } ### ### # Get object for parentCell ### set parentObj [get_bd_cells $parentCell] ### if { $parentObj == "" } { ### puts "ERROR: Unable to find parent cell <$parentCell>!" ### return ### } ### ### # Make sure parentObj is hier blk ### set parentType [get_property TYPE $parentObj] ### if { $parentType ne "hier" } { ### puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." ### return ### } ### ### # Save current instance; Restore later ### set oldCurInst [current_bd_instance .] ### ### # Set parent object as current ### current_bd_instance $parentObj ### ### ### # Create interface ports ### ### # Create ports ### ### # Create port connections ### ### # Create address segments ### ### ### # Restore current instance ### current_bd_instance $oldCurInst ### ### save_bd_design ### } ### create_root_design "" ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/system/system.bd] -top Verilog Output written to : /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v ## if {[string equal [get_filesets -quiet sources_1] ""]} { ## create_fileset -srcset sources_1 ## } ## set top_wrapper $projdir/${design}.srcs/sources_1/bd/system/hdl/system_wrapper.v ## add_files -norecurse -fileset [get_filesets sources_1] $top_wrapper ## if {[llength $hdl_files] != 0} { ## add_files -norecurse -fileset [get_filesets sources_1] $hdl_files ## } ## if {[string equal [get_filesets -quiet constrs_1] ""]} { ## create_fileset -constrset constrs_1 ## } ## if {[llength $constraints_files] != 0} { ## add_files -norecurse -fileset [get_filesets constrs_1] $constraints_files ## } # source ../../common/fpga/system_build.tcl ## if {![info exists design]} { ## set design system ## puts "INFO: Setting design name to '${design}'" ## } ## validate_bd_design INFO: [BD 5-320] Validate design is not run, since the design is already validated. ## write_bd_tcl -force ./${design}_bd.tcl INFO: [BD 5-148] Tcl file written out . ## make_wrapper -files [get_files $projdir/${design}.srcs/sources_1/bd/${design}/${design}.bd] -top INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v ## remove_files -fileset sources_1 $projdir/${design}.srcs/sources_1/bd/${design}/hdl/${design}_wrapper.v ## add_files -fileset sources_1 -norecurse $projdir/${design}.srcs/sources_1/bd/${design}/hdl/${design}_wrapper.v ## if {[info exists oh_synthesis_options]} { ## puts "INFO: Synthesis with following options: $oh_synthesis_options" ## set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1] ## } ## if {[info exists oh_verilog_define]} { ## puts "INFO: Adding following verilog defines to fileset: ${oh_verilog_define}" ## set_property verilog_define ${oh_verilog_define} [current_fileset] ## } ## launch_runs synth_1 INFO: [BD 41-1662] The design 'system.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v Verilog Output written to : /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v Exporting to file /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system.hwh Generated Block Design Tcl file /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl Generated Hardware Definition File /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.hwdef [Wed Sep 5 21:57:54 2018] Launched synth_1... Run output will be captured here: /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.runs/synth_1/runme.log ## wait_on_run synth_1 [Wed Sep 5 21:57:54 2018] Waiting for synth_1 to finish... *** Running vivado with args -log system_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl ****** Vivado v2015.4 (64-bit) **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015 **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source system_wrapper.tcl -notrace Command: synth_design -top system_wrapper -part xc7z020clg400-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 977.293 ; gain = 135.918 ; free physical = 1044 ; free virtual = 39286 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'system_wrapper' [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12] INFO: [Synth 8-638] synthesizing module 'system' [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13] INFO: [Synth 8-256] done synthesizing module 'system' (1#1) [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system.v:13] WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins INFO: [Synth 8-256] done synthesizing module 'system_wrapper' (2#1) [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:12] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1016.668 ; gain = 175.293 ; free physical = 1003 ; free virtual = 39245 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1016.668 ; gain = 175.293 ; free physical = 1003 ; free virtual = 39245 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1228.355 ; gain = 0.000 ; free physical = 830 ; free virtual = 39072 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10287 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.355 ; gain = 386.980 ; free physical = 825 ; free virtual = 39068 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.355 ; gain = 386.980 ; free physical = 825 ; free virtual = 39068 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.355 ; gain = 386.980 ; free physical = 825 ; free virtual = 39068 --------------------------------------------------------------------------------- WARNING: [Synth 8-115] binding instance 'system_i' in module 'system_wrapper' to reference 'system' which has no pins --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.355 ; gain = 386.980 ; free physical = 825 ; free virtual = 39068 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.363 ; gain = 386.988 ; free physical = 825 ; free virtual = 39068 --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.363 ; gain = 386.988 ; free physical = 827 ; free virtual = 39070 --------------------------------------------------------------------------------- Finished Parallel Reinference : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.363 ; gain = 386.988 ; free physical = 827 ; free virtual = 39070 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.363 ; gain = 386.988 ; free physical = 820 ; free virtual = 39062 --------------------------------------------------------------------------------- Finished Parallel Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1228.363 ; gain = 386.988 ; free physical = 820 ; free virtual = 39062 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1283.355 ; gain = 441.980 ; free physical = 761 ; free virtual = 39003 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1283.355 ; gain = 441.980 ; free physical = 761 ; free virtual = 39003 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 753 ; free virtual = 38995 --------------------------------------------------------------------------------- Finished Parallel Technology Mapping Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 753 ; free virtual = 38995 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 753 ; free virtual = 38995 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------+----------+ | |BlackBox name |Instances | +------+--------------+----------+ |1 |system | 1| +------+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |system | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 0| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1292.371 ; gain = 147.391 ; free physical = 752 ; free virtual = 38995 Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 450.996 ; free physical = 752 ; free virtual = 38995 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 13 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 1292.371 ; gain = 379.664 ; free physical = 752 ; free virtual = 38994 report_utilization: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1300.375 ; gain = 0.000 ; free physical = 751 ; free virtual = 38993 INFO: [Common 17-206] Exiting Vivado at Wed Sep 5 21:58:34 2018... [Wed Sep 5 21:58:36 2018] synth_1 finished wait_on_run: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:42 . Memory (MB): peak = 1020.840 ; gain = 8.000 ; free physical = 1230 ; free virtual = 39472 ## open_run synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7z020clg400-1 INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ## report_timing_summary -file timing_synth.log INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs report_timing_summary: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1587.020 ; gain = 382.508 ; free physical = 705 ; free virtual = 38948 ## write_hwdef -force -file "${design}.hwdef" ## set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] ## set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1] ## set_property STRATEGY "Performance_Explore" [get_runs impl_1] ## launch_runs impl_1 [Wed Sep 5 21:58:55 2018] Launched impl_1... Run output will be captured here: /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.runs/impl_1/runme.log ## wait_on_run impl_1 [Wed Sep 5 21:58:55 2018] Waiting for impl_1 to finish... *** Running vivado with args -log system_wrapper.vdi -applog -m64 -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace ****** Vivado v2015.4 (64-bit) **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015 **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source system_wrapper.tcl -notrace Command: open_checkpoint /home/parallella/github/oh_2015.2/src/accelerator/fpga/system.runs/impl_1/system_wrapper.dcp INFO: [Project 1-479] Netlist was created with Vivado 2015.4 INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/parallella/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-604] Checkpoint was created with Vivado v2015.4 (64-bit) build 1412921 open_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1126.961 ; gain = 216.270 ; free physical = 349 ; free virtual = 38591 Command: opt_design -directive Explore INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 4 threads ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. INFO: [Project 1-461] DRC finished with 1 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1173.980 ; gain = 38.016 ; free physical = 342 ; free virtual = 38585 INFO: [Common 17-83] Releasing license: Implementation 11 Infos, 0 Warnings, 1 Critical Warnings and 2 Errors encountered. opt_design failed ERROR: [Common 17-39] 'opt_design' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Wed Sep 5 21:59:10 2018... [Wed Sep 5 21:59:12 2018] impl_1 finished wait_on_run: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:17 . Memory (MB): peak = 1619.035 ; gain = 0.000 ; free physical = 701 ; free virtual = 38944 ## open_run impl_1 ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open while executing "source ../../common/fpga/system_build.tcl" (file "run.tcl" line 12) INFO: [Common 17-206] Exiting Vivado at Wed Sep 5 21:59:12 2018... [ERROR] : Bitstream parsing error !!! Unsupported BIT file cp: cannot stat 'system_wrapper.bit.bin': No such file or directory