In the "parallella gen1 reference", page 38, it is stated that Peak Zynq Frequency is 667 MHz.
The Zynq device used in parallella is XC7Z020-1CLG400C, so this is a -1 speed grade device, the slowest available (yes, I know that some -1 devices can actually operate at -2 or even -3 speed grades, but that is not guaranteed, Xilinx guarantee a -1 device to work at only -1 speed grades).
According to "Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics", page 36: CLB Switching Characteristics, we see that for speed grade -1, the slowest switching time in Table 57 is 1.27 ns which gives a max. freq. of 787.4 MHz. (I do know that different components in the FPGA operate at different freq., e.g. the DSP slices have a max. freq. of 464 MHz, but that's not the point).
The ARM processor operate at 667 MHz.
So it seems that we are operating both the FPGA's and the ARM processors at the same freq. even though the FPGA can reach higher freq., right? (by "FPGA", I am at least referring to the CLB and not to the I/O, DSP Slices, etc, although I know that this is practically not useful).
ali8Statistics: Posted by ali8 — Wed Jul 10, 2013 5:24 am
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