In many cases this will become a lot slower, since traffic is routed all around the chip, but you could setup a router on a far-NORTH-EAST core to route all WEST and NORTH traffic EAST. Effectively disabling WEST-bound write communication on that core (NORTH was already off-chip), but giving that core, erhm let me think, for instance (0x00100000 – 0x80A00000) = 2057 MB of contiguouss DRAM address space. (not entirely true since the DRAM is only 1GB and doesnt extend beyond 0x3FF_FFFFF).
So you could sacrifice this one core to do all your external RAM handling. Not sure in what situations this might be usefull, but the idea is still interesting to me
( O, and I think there might be a copy-paste typo in the architecture reference for the MESHROUTE registers. EAST/WEST/SOUTH settings only influence NORTH-bound traffic according to the desciption....)
DISCLAIMER : I haven't actually played with the board yet, so I might be horribly wrong..
Statistics: Posted by TomV — Wed Dec 03, 2014 11:04 am
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For now I just reached the point where I have a program of my own running on the parallella and epiphany cores, I still have to figure out why the epiphany part is so slow (I need to look at the math optimization flags I think) and why the communications between the cores and the host is not entirely working as intended.
So as you see I still have some work/learning to do before I can really decide whether or not the 32MB are enough for me
Statistics: Posted by schmurfy — Mon Jun 16, 2014 2:22 pm
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