On the E16 Parallella, the emesh addressing hardware could allow upto 52MB contiguous/continuous memory (i.e. addressing anything east of the last core's column address), if the FPGA e-link address logic was changed to allow it through.
But even 52MB is hardly worth the (significant) effort of rebuilding the FPGA, kernel, U-Boot, etc.
What is required is what shodruck called a "memory hole remapper" to circumvent the hardware feature. That includes Epiphany library routines for external memory access (read/write/DMA) that allow user code to 'see' a continuous external memory space, but perform the physical address translation for the emesh hardware. FPGA e-link logic would translate the addresses back to the real contiguous SDRAM memory.
I did some work on this (see topic ) while waiting for my boards to arrive. At that point, Andreas dangled that cryptic promise about something new in the pipeline, so I'm now (still) waiting to see what that could be .....
Cheers,Statistics: Posted by greytery — Fri Nov 07, 2014 5:23 pm
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