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Parallella Community Supercomputing for Everyone 2017-01-22T15:25:25+00:00 https://parallella.org/forums/feed.php?f=13&t=3975 2017-01-22T15:25:25+00:00 2017-01-22T15:25:25+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18530#p18530 <![CDATA[Re: Help ! Odd in core memory behaviour or my mistake.]]>
Sorry every one that looked at this post.

Thank you sebraa for your time.

Look at my mistake:

https://github.com/joseluisquiroga/para ... -test-16ok

What was happening was that the initial branch (addr zero, SYNC interrupt) was not been executed (it was not declared as "ax" section) so the sp was NOT been initialized by my asm code in "normal_start" resulting in a shared mem addr for the stack.... so aux var was in shared mem ..... I forgot I had that mistake in my early tests and reused old code to do some simple ones ...

Sorry every one again.

That is what happens when you "muck around" with the start code...

JLQ.

Statistics: Posted by joseluisquiroga — Sun Jan 22, 2017 3:25 pm


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2017-01-22T14:08:25+00:00 2017-01-22T14:08:25+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18529#p18529 <![CDATA[Re: Help ! Odd in core memory behaviour or my mistake.]]> Statistics: Posted by sebraa — Sun Jan 22, 2017 2:08 pm


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2017-01-20T17:09:00+00:00 2017-01-20T17:09:00+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18527#p18527 <![CDATA[Re: Help ! Odd in core memory behaviour or my mistake.]]> Statistics: Posted by joseluisquiroga — Fri Jan 20, 2017 5:09 pm


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2017-01-20T03:42:40+00:00 2017-01-20T03:42:40+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18526#p18526 <![CDATA[Re: Help ! Odd in core memory behaviour or my mistake.]]> Statistics: Posted by joseluisquiroga — Fri Jan 20, 2017 3:42 am


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2017-01-20T03:40:40+00:00 2017-01-20T03:40:40+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18525#p18525 <![CDATA[Re: Help ! Odd in core memory behaviour or my mistake.]]> Statistics: Posted by joseluisquiroga — Fri Jan 20, 2017 3:40 am


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2017-01-19T19:31:43+00:00 2017-01-19T19:31:43+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18523#p18523 <![CDATA[Re: Help ! Odd in core memory behaviour or my mistake.]]> especially if you go off-chip (i.e. shared memory), the memory ordering is relaxed. Reads following writes to off-core destinations happen in a non-deterministic order. (I don't know if this applies for on-core transactions through a global address, though.)

Your assembly code does not match your source code (incomplete), the build instructions and the used linker script are missing. Since you muck around with the startup code, I simply assume that ".data" and/or ".bss" are not allocated within local memory, and the behaviour you see is permitted by the Epiphany.

Statistics: Posted by sebraa — Thu Jan 19, 2017 7:31 pm


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2017-01-19T12:32:29+00:00 2017-01-19T12:32:29+00:00 https://parallella.org/forums/viewtopic.php?t=3975&p=18519#p18519 <![CDATA[Help ! Odd in core memory behaviour or my mistake.]]>
This few lines program behaves very unexpected:

https://github.com/joseluisquiroga/para ... _prog_16.c

I would like some feedback:

Do you get the same results? (value 0xddd at the end)
Is it just my parallela board?
Can you explain the behaviour?

Thanks.

JLQ.

Statistics: Posted by joseluisquiroga — Thu Jan 19, 2017 12:32 pm


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