The variable name "tailEnds" is perhaps not a good one. It is the amount of data for the core modulus the buffer size. I'll make sure that it waits before sending the results back.
Do the processor states in the debug session shed any light on what is happening? I looked through the architecture reference and there is a lot of discussion about processor states but no table that relates the mnemonic with the value.
I'm getting into dma in the belief that it can be used to shift one lot of data around while the core is processing another. If the algorithm is non-trivial or needs to be run many times (e.g. neural network training) then there is a net gain, even if the data transfer is not as quick as it could be. Am I on the right track here?
nickStatistics: Posted by nickoppen — Tue May 16, 2017 10:52 am
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