Statistics: Posted by notzed — Mon Feb 04, 2013 6:57 am
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Getting nice high res pictures is actually a bit of a challenge. We use nine metal layers on our chip, with the top layer being dedicated to supplies. Unless we etch away the toplayer, the picture will just look like a boring plate of metal and not at all like the fancy die shots you would generally see from BigCo. We could go ahead and spend some money/time to get it done, but that will have to wait. In the meantime, here is a picture of our 16-core wirebond package (with the die in the middle).
Statistics: Posted by aolofsson — Tue Jan 15, 2013 3:01 am
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If I understood correctly, some of the cost optimization comes from manufacturing more chips per wafer.
I was wondering if they were manufactured with the exact same caracteristics ( 65nm / 1GHz clock ) and just more per wafer (larger wafer ?) or if they were going to be smaller technology.
In anycase, waiting for pictures of the die in high res :p
Cheers,
Sylvain
Statistics: Posted by tnt — Mon Jan 14, 2013 6:08 pm
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