Andreas
Statistics: Posted by aolofsson — Fri Aug 22, 2014 12:45 pm
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I'm using the headful 7010 image, which I downloaded on 25th of july with the supplied plugpack, rev1.1 board i believe.
I seem to be seeing writes changed to writes of 0; well i'm definitely seeing that, i don't know if that's the only problem. It is much worse when the cores are busy accessing external ram (via dma or not) which would match the description above; i.e. if i add a printf in the loop which does the writing.
Changing the order of the writes around a bit and using fewer cores "fixes" it, but only because everything is running synchronous, but it's basically the same problem I hit before with the rev0 board.
Statistics: Posted by notzed — Fri Aug 22, 2014 11:19 am
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tnt is right, no need to panic
After some testing and debug we concluded that there may be a problem with the FPGA logic. We are still looking for the root cause.
In certain scenarios, e-write transactions from the host, targeted at the eCore's memory, get lost on the way, when there is an external DMA process running from the device.
For now, please use a work protocol a-la matmul demo, where communication from host to chip, when external DMA is involved, is done via mailboxes in the external memory. AFAICT, there is no problem working this way.
Statistics: Posted by ysapir — Wed May 08, 2013 1:45 pm
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