Inside the Epiphany, bandwidth is generally sufficient (our problem is the memory size and as a consequence of too little buffering, latency; not data throughput). To my understanding, the NoC routers queue at most one transaction per direction. So, if your top-left core writes many packets to shared memory, then these transactions will queue up at each affected intersection and basically kill all traffic on that path. So it is probably beneficial to designate the bottom right core for off-chip (shared memory) transactions.Statistics: Posted by sebraa — Fri Nov 20, 2015 3:33 pm
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