I have another question:
Written in the article about the network topology: "Transactions move through the network, with a latency of 1.5 clock cycles per hop. A transaction traversing from the left edge to right edge of 64-core chip would thus take 12 clock cycles."
Am I right that this message implies that the network operates on rising-edge AND falling-edge? Like a DDR-RAM?
Otherwise i can't explain to myself the half clock cycle?!
Kind regards,
mxStatistics: Posted by mxfreak — Thu Mar 13, 2014 2:08 pm
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