Statistics: Posted by aolofsson — Thu Oct 09, 2014 8:41 pm
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I agree with both of you.
1.) To improve modularity and collaboration we should definitely give more guidance on how to add/customize FPGA logic to play nicely with the Epiphany.
2.) The current FPGA design is really just a first stab at a Parallella system design and it's not optimal. Things will really get interesting when folks start streaming data through the PEC_GPIO interface and I am convince that we will need to redesign the FPGA system at that time. Still lots of open questions regarding what the micro-archtiecture should look like. The Zynq has a lot of cool features that we haven't had time to use yet.
3.) Eventually we hope to have a solid Parallella reference design where folks could easily "put code" here and be up and running with their own optimal custom Parallella loads quickly.
Examples from our "todo" list for FPGA logic:
1.) We currently don't use the cache coherent AXI port. (might be useful for some..)
2.) Interrupt inputs to ARM system from FPGA logic (chapter 7 of Zynq TRM)
3.) How to use the DMA (make e-hal faster). (see chapter 9 of Zynq TRM)
4.) Increase speed of FPGA logic
5.) Full cross bar allowing communication between Epiphany and GPIO directly.
6.) Implement a custom Epiphany DMA engine in PL to avoid eLink read penalty.
Andreas
Statistics: Posted by aolofsson — Sat Aug 17, 2013 3:49 pm
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