With 64 core chips you loose more cores of that theoretical 4k space as not having row 0 means not having other rows as well.
You also need some addressable space to communicate with external components.
External communication with square layout is already reduced because of routing limitations.
Statistics: Posted by ticso — Thu Aug 29, 2013 4:47 pm
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Your "magical" unregister of a core just doesn't make much sense in the current chips and it would imply quite a bit of logic in each router node to know and keep track of this. Any way to grow beyond the current model would need to sacrifice the 'uniform' address space view and would most likely be implemented by translation layers between 'islands' of cores, avoiding to modify the mesh and cores themselves and just adding logic at the edge of large groups of them.
Statistics: Posted by tnt — Thu Aug 29, 2013 4:05 pm
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Statistics: Posted by Gravis — Thu Aug 29, 2013 3:42 pm
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Statistics: Posted by LamsonNguyen — Tue Aug 27, 2013 6:19 am
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