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Parallella Community Supercomputing for Everyone 2018-11-07T00:47:29+00:00 https://parallella.org/forums/feed.php?f=49&t=3411 2018-11-07T00:47:29+00:00 2018-11-07T00:47:29+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=20100#p20100 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]>
https://seguridad-agile.blogspot.com/20 ... nutos.html

Statistics: Posted by cpantel — Wed Nov 07, 2018 12:47 am


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2018-10-18T22:19:48+00:00 2018-10-18T22:19:48+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=20089#p20089 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]>
booting with the new bitstream, I mounted the BOOT partition and:

cat /mnt/parallella.bit.bin > /dev/xdevcfga

and there was no timeout.


update 2:

root@parallella:/lib/modules/4.6.0+# find . -iname epi*
./kernel/drivers/misc/epiphany.ko

root@parallella:~# grep --color=never -i epi config
CONFIG_EPIPHANY=m
# CONFIG_DEBUG_TIMEKEEPING is not set

root@parallella:~# modmod epiphany
root@parallella:~# lsmod
Module Size Used by
epiphany 19123 0


seems that I am only a mknod away from success!!

but can not find the mknod /dev/epiphany ..... ..... ....


update 3:

Perhaps I am too tired or there is an erratic behavior.

I boot from a non-modified BOOT and /dev/epiphany shows up, but it is a folder

ls /dev/epiphany/
elink0 mesh0

could it be that it is too modern for the 15 minutes example?

BTW, there are the major and minor numbers...

ls /dev/epiphany/ -al
total 0
drwxr-xr-x 2 root root 80 Aug 18 00:04 .
drwxr-xr-x 13 root root 3280 Aug 18 00:05 ..
crw-rw-rw- 1 root root 243, 0 Aug 18 00:04 elink0
crw-rw-rw- 1 root root 243, 1 Aug 18 00:04 mesh0


I guess that I need an older kernel

Statistics: Posted by cpantel — Thu Oct 18, 2018 10:19 pm


]]>
2018-10-18T22:11:38+00:00 2018-10-18T22:11:38+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=20088#p20088 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]>
Finally, I closed my eyes and zen picked a commit near master that just worked (258cda9). Then, kind of bisected (70a6f14,2f91330, fbfe559, afccd4a, ee2e234) towards master until the the last working commit (afccd4a).




It seem ok till now.

1) First question:

when I tried the xdevcfg method, it seems to timeout

cat parallella.bit.bin > /dev/xdevcfg
cdns-i2c e0004000.i2c: timeout waiting on completion
cdns-i2c e0004000.i2c: timeout waiting on completion
cdns-i2c e0004000.i2c: timeout waiting on completion
...

it is normal? I left it two minutes, I do not think so.


2) I burned the bitstream in the BOOT partition, compiled driver.c and test.c ok, but when run, it fails:

f_map: No such file or directory
Segmentation fault

when tries to open /dev/epiphany, that does not exist.

[driver.c]
//Open /dev/mem file if not already
if(mem_fd < 1) {
mem_fd = open ("/dev/epiphany", O_RDWR);
if (mem_fd < 1) {
perror("f_map");
return -1;
}
}


I saw viewtopic.php?f=48&t=1528, but it seems to old (2014), it should've failed with the 15 minutes example (2016-2017)

My uname -a:

Linux parallella 4.6.0+ #1 SMP PREEMPT Wed Dec 7 13:27:40 CET 2016 armv7l armv7l armv7l GNU/Linux

Any hints or advice?

Statistics: Posted by cpantel — Thu Oct 18, 2018 10:11 pm


]]>
2018-10-08T01:45:56+00:00 2018-10-08T01:45:56+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=20085#p20085 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]>
About the branch:

If I checkout "stable", the landscape changes far beyond my little current knowledge.

Anyway, I will try this way, in a few days (weeks?) I'll tell you.


About the versions:

~/Xilinx/Vivado/2015.2/bin/vivado -version
Vivado v2015.2 (64-bit)
SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.


./Xilinx/Vivado/2015.4/bin/vivado -version
Vivado v2015.4 (64-bit)
SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015

thank you

Statistics: Posted by cpantel — Mon Oct 08, 2018 1:45 am


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2018-09-27T02:00:33+00:00 2018-09-27T02:00:33+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=20082#p20082 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by olajep — Thu Sep 27, 2018 2:00 am


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2018-09-06T01:07:14+00:00 2018-09-06T01:07:14+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=20072#p20072 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by cpantel — Thu Sep 06, 2018 1:07 am


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2016-08-31T12:47:52+00:00 2016-08-31T12:47:52+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=17953#p17953 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by Melkhior — Wed Aug 31, 2016 12:47 pm


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2016-08-31T06:43:03+00:00 2016-08-31T06:43:03+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=17951#p17951 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by peteasa — Wed Aug 31, 2016 6:43 am


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2016-08-28T10:38:47+00:00 2016-08-28T10:38:47+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=17940#p17940 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by Melkhior — Sun Aug 28, 2016 10:38 am


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2016-01-25T23:19:27+00:00 2016-01-25T23:19:27+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=16666#p16666 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by aolofsson — Mon Jan 25, 2016 11:19 pm


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2016-01-25T23:02:38+00:00 2016-01-25T23:02:38+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=16665#p16665 <![CDATA[Re: Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by theover — Mon Jan 25, 2016 11:02 pm


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2016-01-21T20:50:10+00:00 2016-01-21T20:50:10+00:00 https://parallella.org/forums/viewtopic.php?t=3411&p=16647#p16647 <![CDATA[Creating an FPGA accelerator in 15 minutes]]> Statistics: Posted by aolofsson — Thu Jan 21, 2016 8:50 pm


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