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[ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/includes/bbcode.php on line 112: preg_replace(): The /e modifier is no longer supported, use preg_replace_callback instead [phpBB Debug] PHP Warning: in file [ROOT]/feed.php on line 173: Cannot modify header information - headers already sent by (output started at [ROOT]/includes/functions.php:3823) [phpBB Debug] PHP Warning: in file [ROOT]/feed.php on line 174: Cannot modify header information - headers already sent by (output started at [ROOT]/includes/functions.php:3823) Parallella CommunitySupercomputing for Everyone2014-09-23T08:46:20+00:00https://parallella.org/forums/feed.php?f=51&t=11542014-09-23T08:46:20+00:002014-09-23T08:46:20+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=10894#p10894<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]> I think the lack of pinmuxing is a very unfortunate limitation of the Zynq, and one which could be quite effectively resolved.
Statistics: Posted by yanidubin — Tue Sep 23, 2014 8:46 am
]]>2014-06-19T07:40:44+00:002014-06-19T07:40:44+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=8594#p8594<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]> From Linux the infrastructure for pin muxing is already in the kernel:
The driver and FPGA backend for it should be simple, just a few registers to set the function of each pin, with GPIO as default. If there is not enough logic available to mux it to any pin, it should be at least possible to disable it and use the GPIO function for a pin. But if the FPGA has still some room, you could fill it up with as many SPI, CAN etc. modules as you want.
Statistics: Posted by frank_buss — Thu Jun 19, 2014 7:40 am
]]>2014-05-07T19:27:57+00:002014-05-07T19:27:57+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7319#p7319<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by parapara — Wed May 07, 2014 7:27 pm
]]>2014-05-07T19:26:14+00:002014-05-07T19:26:14+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7318#p7318<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by parapara — Wed May 07, 2014 7:26 pm
]]>2014-05-06T06:45:33+00:002014-05-06T06:45:33+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7275#p7275<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by 9600 — Tue May 06, 2014 6:45 am
]]>2014-05-06T03:35:17+00:002014-05-06T03:35:17+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7273#p7273<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by FHuettig — Tue May 06, 2014 3:35 am
]]>2014-05-05T23:53:22+00:002014-05-05T23:53:22+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7270#p7270<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by rec — Mon May 05, 2014 11:53 pm
]]>2014-05-05T22:45:33+00:002014-05-05T22:45:33+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7268#p7268<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]> The control lines would be raw signals without a buffer chip like Tx and Rx have on the board, so some care might be needed.
I like the sound of Fred's I2C idea.
Tim
Statistics: Posted by timpart — Mon May 05, 2014 10:45 pm
]]>2014-05-06T03:14:14+00:002014-05-05T21:05:12+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7263#p7263<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by FHuettig — Mon May 05, 2014 9:05 pm
]]>2014-05-05T20:38:18+00:002014-05-05T20:38:18+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7259#p7259<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by 9600 — Mon May 05, 2014 8:38 pm
]]>2014-05-05T18:27:23+00:002014-05-05T18:27:23+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7248#p7248<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by FHuettig — Mon May 05, 2014 6:27 pm
]]>2014-05-04T12:43:24+00:002014-05-04T12:43:24+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7220#p7220<![CDATA[Re: Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by parapara — Sun May 04, 2014 12:43 pm
]]>2014-05-04T11:17:32+00:002014-05-04T11:17:32+00:00https://parallella.org/forums/viewtopic.php?t=1154&p=7217#p7217<![CDATA[Routing additional Zynq hard block I/O to PEC_FPGA]]>Statistics: Posted by 9600 — Sun May 04, 2014 11:17 am
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