Any how, non-demanding little extra state machines should get verilog/vhdl compiled in good enough, which I too find an interesting thing to work on. It may be, that for certain experiments, it can be automated what logic is created by an external tool like my flow simulator, and also the communication with the additional FPGA logic can probably be automated, like on the bottom of this page:
My main interests would lie in the making of serious additional FPGA computations, utilizing DSP IPs and FPGA FFT IPs, and on the other end, I'm formally educated in Network Theory after all, it would be very cool to try to let the Epiphany act as new parallel LISP processor, aided by the FPGA, but only to actually compute faster than a PC can, for instance.
I'm afraid that would take quite a bit of work beyond most BSc EEs, and isn't very profitable at the moment...
T.Statistics: Posted by theover — Mon Jun 16, 2014 8:01 pm
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