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But up to now I've actually been focusing entirely on the Epiphany. I was planning to wait for the update to Vivado before turning my attention to the Zynq. But if that is still some way off, then an idiot's guide to getting started with ISE and the Parallella would certainly be welcome.
Statistics: Posted by cmcconnell — Tue Sep 23, 2014 1:44 am
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As to your other points, I think I may have to disappoint you, since you probably need an expert (which I am not). At present, I can't satisfy your curiosity about performance, but in time this may change.
Also, at this stage I only intend to cover the most basic way of interfacing from the Linux side (/dev/mem, rather than writing a dedicated driver to interact with the registers, and adding interrupts - I believe this is quite possible). I'm putting off writing drivers until I get AXI-stream working (a high performance DMA based mechanism), which is what I have been aiming for all along, however success with this has eluded me thus far (and it is currently on the backburner while I write this stuff up, and then get back to work on my robotics project - but sooner or later someone, maybe myself, will get this working).
There are two reasons I haven't tested the bandwidth of what I've implemented - firstly, it isn't a high performance interface, and I always intended to produce the FPGA equivalent of the matmul example - but I wanted to show the FPGA to advantage there. Secondly, I doubt using /dev/mem rather than a dedicated driver is the most efficient way to access this - but haven't looked into the options here.
As I'll state in my tutorial, these are just my learnings from tutorials for the Zedboard/Zync over the last few weeks in general presented in a digestible format for the Parallella with various hurdles smoothed over. I'm not presenting these because I am an expert (I did minimal VHDL during my EE degree, and this was 7yrs ago already - I'm tinkering with the FPGA to flake off the rust, improve those skills, then put them to use). Since enough people have registered interest in getting a leg up on this stuff, my aim then is to lower the barrier to entry (by giving a Parallella tailored intro), and once people start interacting with the FPGA, then they can (and should) go elsewhere and learn from more general tutorials. Hopefully we'll see more people discussing the FPGA stuff in the forums (not that I want to take attention away from the Epiphany - each has its place).
Statistics: Posted by yanidubin — Mon Sep 22, 2014 10:54 pm
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So I would be most helped with an example like: here's the Epiphany interface so-and-so, these address ranges are free, the handler can be added and compiled here or so-ana-so, and the glue holds if these and these conflics are prevented. The rest is dancing about trivialities I don't care for,but maybe others do.
T.
Statistics: Posted by theover — Mon Sep 22, 2014 2:14 pm
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Thanks very much, I will have a look and see.
All the best
Andy
Statistics: Posted by AndyC — Mon Sep 22, 2014 2:01 pm
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Okay, I had a quick look at a diff of a good working project versus what I got on a fresh project.
It seems on both my AXI4Lite and AXI4 projects, I am using the other bus interface, which is not enabled by default. That is, M_AXI_GP0 rather than M_AXI_GP1.
The difference in the system.mhs which I think is relevant is:
< BUS_INTERFACE M_AXI_GP1 = axi_interconnect_1
---
> PARAMETER C_USE_M_AXI_GP0 = 1
> BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
I spent some time comparing the XPS sources between Parallella and Zedboard working that one out. I can't remember why I concluded this was needed.
I don't like giving directions without testing them myself, but it is late and I think there is a good chance this may sort you out. Good luck, and I will definitely get to the bottom of it tomorrow if this does not resolve it for you
You can implement these changes by just editing your file (easiest) - or you can double click 32b GP AXI Master Ports at the lower left of the system diagram (The one on the Zynq tab in XPS) and enable GP0, then go to the Bus Interfaces tab and assign axi_interconnect_1 to M_AXI_GP0.
Statistics: Posted by yanidubin — Mon Sep 22, 2014 1:33 pm
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I have had no luck at all adding AXI peripherals to the headless 7020 project while it works fine in the 7020 hdmi project.
I get the following warnings:
[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_???' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:6]
[Constraints 18-11] Could not find cell or net 'axi_interconnect_1/*_converter_bank/*clock_conv_inst/*asyncfifo_*/*mem/*dout_i_????' [C:/Development/parallella/Fpga/parallella-hw/fpga/edk/parallella_7020_headless/implementation/system_axi_interconnect_1_wrapper.ncf:7]
If I run through the implementation and generate the bitstream it loads ok but when I try to read from the AXI bus from a linux app the parallella hangs totally, so I guess these warnings are important.
Did you do anything special setting the AXI bus up?
Cheers
Andy
Statistics: Posted by AndyC — Mon Sep 22, 2014 12:37 pm
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This is my first blog / public tutorial, and I'm struggling with the limitations of free wordpress (no scripting, very little customisation - despite what, I gather, wordpress offers when properly hosted). As I don't have my own hosting as such, this will have to do for now.
Any feedback is welcome. I am already aware that brevity is not my strong point.
Statistics: Posted by yanidubin — Mon Sep 22, 2014 12:33 pm
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Have you managed to add the axi peripherals to the headless project or just the hdmi one?
Cheers
Andy
Statistics: Posted by AndyC — Mon Sep 22, 2014 12:11 pm
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Cheers,
Andrew
Statistics: Posted by 9600 — Sun Sep 21, 2014 12:21 pm
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If there is interest, I would be willing to write a tutorial showing the steps to use in the wizard, the diffs showing helpful modifications to take the output of this and alter it so you can write a value and get a result back to show the FPGA has worked on the data. I can also include an example python test script to exercise the core (write value, read result, and compare to ensure correctness). I'll either include the process for runtime reconfiguration of the FPGA as instructions or part of the script.
The two interfaces I have been successful with use the /dev/mem memory mapped IO. This is the most basic approach which requires no development of your own driver kernel module.
I can cover both, since there is very little difference other than the checkboxes in the wizard.
The first uses AXI4Lite to expose a bunch of registers. To brush up on my VHDL, implemented a basic ALU, giving each of the registers an operand/instruction/result role.
The second uses full AXI4, and provides a means to write values to /dev/mem, and have them pulled into BRAM on the FPGA. After testing this with the same ALU, I decided to make an application which made use of the expanded addressable memory space provided - so I'm still perfecting a smoothing filter which runs on an 8x8 matrix of 8-bit grayscale pixel values and returns the result.
Would you (or anyone?) be interested? I believe I could have something up within a week or so.
Statistics: Posted by yanidubin — Sat Sep 20, 2014 10:31 am
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