For audio purposes, it is handy to be able to very quickly change one FPGA setup for another, for instance containing different sound generators but I would like to cover the basis a bit. So: when changing the FPGAs programming "on the fly" (like from a script under User Interface control) of course we need to know at which point in time buffers are empty, IO pins have returned to some predefined state, and maybe some preparations for the logic circuit to change have to be taken (for instance lowering the volume or smoothly setting to zero DACs for audio purposes).
At this point, this is a Parallella idea, not primarily including the Epiphany, because that adds t the complexity, takes some AXI resources maybe available to example projects, and there's always the option to change the FPGA back to the original situation (I suppose currently the 2015.1 design) by pushing the normal bit.bin file through the programming device. So I presume I make sure all Epiphany activity is done, maybe run the "low power" program from the supplied sources, and with the to be loaded in FPGA bit file simply ignore the Epiphany inputs and set the outputs to zero or floating (3 state) conditions.
My questions to maybe some of you savvy people about the things Epiphany are: is that ok for the Epiphany chip, to ignore data, set the clock disable bit (or give it no clock at all)?
Also, suppose the Epiphany has been disconnected for the time being from the FPGA's activities, what's the way to send data down the AXI interface, I recall there was a mmap() call to do that as superuser in the beginning, but now that there's a normal Linux user based interface: how does that work, is there some page on that ? It's a shame if all that works get's not used, I guess, and Xilinx documentations doesn't talk about the Linaro Linux programming.
Anyhow, I think it can be good fun to make simple (fast FPGA compile time) projects like audio generator, frequency counter, led control, etc that can be loaded into the Parallella with an easy to use script for testing out logic circuits, but there needs to be communication with the Zinq's ARM cores!
I make it sound simple, because I've not got the time or the acquired skills to play around with the whole Zinq design in a short time, but I do have serious applications in mind, where the basis computations on the FPGA are a sequence of measurement, synthesis and correction of high frequency audio signal paths in practical use that cannot be easily achieved with other means. Short turnaround times of the Vivado compile are handy, and the idea of relative simple repetition of various primitives instead of painstakingly made complete hardware designs that are actually only needed for certain phases of computations that aren't normally combined.
Theo V.Statistics: Posted by theover — Sat Oct 24, 2015 4:56 pm
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