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Parallella Community Supercomputing for Everyone 2016-05-31T11:00:25+00:00 https://parallella.org/forums/feed.php?f=51&t=3376 2016-05-31T11:00:25+00:00 2016-05-31T11:00:25+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=17685#p17685 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]>
Maybe it will be interesting to try simple things like creating a memory module in the FPGA (in C that should be easy) that can be read from a Zynq/ARM C program, and some other types of AXI access to FPGA that might come in handy. Also it would be interesting to make a C program able to communicate with user pins, I've not done that yet. There are examples with the Vivado HLx version that tackle all kinds of C programs that compile proper, and the latest version, which I logged in some other thread about that I tried, does good C to Verilog simulation comparisons that appear to work in the free version.

Did anyone else get into this subject, or is it considered to spooky to mess with C-to-FPGA compilation ?

I know the Verilog it creates is sketchy, contains lots of unoverseeable assignments (at least the previous vivado_hl did), isn't efficient in every way, and even using one trigonometric function can create more HDL than fits in my 7010 board, but still, it's interesting to after the times of Silicon Valley and the Mead & Conway book finally be able to program a sea of gates using an actual silicon compiler. It should even be easy to put the whole Parallella project FPGA in C, at least as a lot shorter program than the HDL defs...

T.

Statistics: Posted by theover — Tue May 31, 2016 11:00 am


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2016-01-06T08:46:31+00:00 2016-01-06T08:46:31+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16537#p16537 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]>
Regarding your comment about cache, it doesn't really make any difference. Here is why:

1. UIO driver disables caching on memory it exposes to user-space. It's a sensible approach since most of the time you don't want cache coherency get in the way, if you care about efficiency you write custom driver anyway, and not use generic_uio.

2. Cache line on Zynq is 32 bytes wide, which is 8 4-byte registers. Assuming register 0 is cache aligned (has to be anyway), all 8 registers fit into 1 cache line. So even if you use custom driver that doesn't disable caching and use cache-cherent interface to the PL, using registers 0,1 vs 4,6 won't make a difference throughput-wise.

Statistics: Posted by kirill — Wed Jan 06, 2016 8:46 am


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2016-01-05T18:44:15+00:00 2016-01-05T18:44:15+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16534#p16534 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]>
But, with the above changes,to put it mild: IT WORKS, so I happily have device tested my first automated C-to-FPGA on the Parallella board.

T.

Statistics: Posted by theover — Tue Jan 05, 2016 6:44 pm


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2016-01-05T11:44:22+00:00 2016-01-05T11:44:22+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16533#p16533 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]> Statistics: Posted by kirill — Tue Jan 05, 2016 11:44 am


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2016-01-05T01:06:40+00:00 2016-01-05T01:06:40+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16526#p16526 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]> Statistics: Posted by theover — Tue Jan 05, 2016 1:06 am


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2016-01-03T14:33:55+00:00 2016-01-03T14:33:55+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16521#p16521 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]> Statistics: Posted by theover — Sun Jan 03, 2016 2:33 pm


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2016-01-03T13:04:01+00:00 2016-01-03T13:04:01+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16520#p16520 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]> Statistics: Posted by kirill — Sun Jan 03, 2016 1:04 pm


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2016-01-02T23:03:56+00:00 2016-01-02T23:03:56+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16518#p16518 <![CDATA[Re: Xilinx Webpack 2015.4 HLx edition]]> Statistics: Posted by theover — Sat Jan 02, 2016 11:03 pm


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2015-12-29T13:52:30+00:00 2015-12-29T13:52:30+00:00 https://parallella.org/forums/viewtopic.php?t=3376&p=16491#p16491 <![CDATA[Xilinx Webpack 2015.4 HLx edition]]> Statistics: Posted by theover — Tue Dec 29, 2015 1:52 pm


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