I'm having some trouble getting the PL clocks to work (e.g. FCLK_CLK1). All I want is to route it to an I/O pin to use it with external hardware. I got a similar design running on a zedboard just fine, but I read that it is different on a Parallella. Apparently, the PL fabric clock configuration (FCLK_CLK0..3) is made in the PS. I saw people saying this gets configured in the FSBL, but on the Parallella, I don't have access to the FSBL because the operating system is loaded directly by the on-board u-boot bootloader and not the custom FSBL on the SD card. If this all is correct, I would have to change the clocks from the PS, but how do I do that? I don't think there can be much wrong with my design, as I am basically just routing a signal to an I/O and the other signals I have routed to an I/O are working fine. Or is there an additional step I might have missed?
ThanksStatistics: Posted by a_k — Wed Feb 17, 2016 9:52 am
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