ug871-vivado-high-level-synthesis-tutorial.pdf
and part of the manual in:
ug902-vivado-high-level-synthesis.pdf
And after trying some of the examples and having loaded a few examples in the existing Parallella project referenced above, it is safe to say there is serious potential in Vivado2016.1 + Vivado_HLS to get a C function to act as a piece of FPGA code that can also be connected up to the AXI (in my case "lite") bus to communicate with the Zynq's ARM cores.
The Tcl interpreter in Vivado can be extended with external code, the IP library is considerable and contains powerful blocks (like FFT, Cordic, memory constructs, etc. etc that in this version mostly are free to use for Webpack users ! That's a big thumbs up for Xilinx! The RTL simulator also works both in _hlx and the main vivado (though I don't know if it is possible to connect with the "logical analyze" block that is available from the IP lib), and the C code cross check compilation and C versus hardware compiled C compilation and simulation works smooth and efficient.
So after doing some of the tutorial examples in practice I want to try if, with the right directives, a C function can also be used to do user IO and connections with self-made IP blocks.
Anyhow, it's recommended for those into the Zynq as fast(-er) turnaround prototype machine.
T.Statistics: Posted by theover — Tue Jun 21, 2016 2:38 pm
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