But I noticed this when compiling: "43 Infos, 102 Warnings, 100 Critical Warnings and 0 Errors encountered.". In my FPGA designs I always try to reduce this to 0 warnings, which is not always possible, but 100 critical warnings is a lot. Most of them looks easy to solve, like some unknown property name. The advantage of having only a handful of warnings is that you don't miss the important ones
Any plans to port it to Vivado 2017.2?
Statistics: Posted by frankbuss — Wed Aug 09, 2017 4:36 pm
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Now, last week I started upgrading the parallella to linux 4.4 and Vivado, but without success.
What I did was:
- get the latest SD image with ubuntu 15.04, install and run it. All went Ok, but of course my peripherals weren't there.
- recompile and reflash the u-boot from the ESDK 2016.3 (for running the UART at 921600). All Ok.
- replace the kernel and device tree with those from my 4.4.20 version. Still all Ok.
- download and install Vivado 2014.3 Webpack under linux (note that I use mageia 4, shouldn't matter).
- get the latest(?) FPGA from the parallella-hw archive and, not changing anything, rebuild with vivado 2014.3 following your instructions.
all went smoothly.. well, almost; see the warning below.
Put the bitfile on the SD card, restart and... the kernel hangs accessing the Epiphany (I know because it works if I remove the Epiphany driver, and also by comparing the logs).
To be sure I restored your kernel, and the system still hangs. So it's either the FPGA sources, or Vivado, or Vivado under linux.
Now for the critical warnings I got from Vivado 2014.3:
CRITICAL WARNING: [Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.
CRITICAL WARNING: [Memdata 28-148] Could not complete initialization of processor data. Could not create the file: /usr/local/parallella/parallella_7020_headless/parallella_7020_headless_gpiose_elink2.runs/impl_1/elink2_top_wrapper.mmi
There was another warning about a mismatch in MASTER_TYPE between BRAM and axi_ctrl, or something similar, but I can't find it in the logs.
Questions:
how did you generate the FPGA bitfile on the official SD? Are these sources available? And where?
could these warnings be the cause of the missing Epiphany interface? Are they linux-specific? And how to correct them?
BTW, why some of the epiphany tests in your SD card under /home/parallella fail to build, or fail to execute?
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Update: Vivado 2014.3.1 under Windows gives exactly the same warnings and produces the exactly same bitfile, which of course doesn't work.
Statistics: Posted by avignani — Fri Sep 16, 2016 11:20 pm
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