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Parallella Community Supercomputing for Everyone 2017-08-16T22:43:00+00:00 https://parallella.org/forums/feed.php?f=51&t=4068 2017-08-16T22:43:00+00:00 2017-08-16T22:43:00+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19487#p19487 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]>
https://github.com/FrankBuss/oh/commit/ ... 807ceceefb

The system_bd.tcl file was just re-created by Vivado as suggested from the script, with "write_bd_tcl" on the Tcl command line. I guess it would be as easy with the parallella project.

BTW, I noticed the OH components are very unfinished, like there is a lot of empty modules and skeleton code. Is this project still alive and do people write code for it? Personally I don't like Verilog, I prefer VHDL. But recently I discovered Chisel ( ), which makes it much easier to write HDL programs, because it has the power of Scala as the backend. For example exhaustive testbenches are much simpler to write and run. Or need a ROM with a sin-table? No problem with a real language like Scala, just one line to generate it inline for the synthesizing step. This might be a better base for the OH framework.

Statistics: Posted by frankbuss — Wed Aug 16, 2017 10:43 pm

]]> 2017-08-12T03:46:13+00:00 2017-08-12T03:46:13+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19470#p19470 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]> Statistics: Posted by frankbuss — Sat Aug 12, 2017 3:46 am

]]> 2017-08-09T14:48:02+00:00 2017-08-09T14:48:02+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19457#p19457 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]> Statistics: Posted by olajep — Wed Aug 09, 2017 2:48 pm

]]> 2017-08-08T08:47:59+00:00 2017-08-08T08:47:59+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19452#p19452 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]> Statistics: Posted by adexmont — Tue Aug 08, 2017 8:47 am

]]> 2017-08-08T06:39:05+00:00 2017-08-08T06:39:05+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19451#p19451 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]> Statistics: Posted by frankbuss — Tue Aug 08, 2017 6:39 am

]]> 2017-08-06T13:12:15+00:00 2017-08-06T13:12:15+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19447#p19447 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]> I cloned parallella-fpga github repository and installed vivado 2017.2 web (free) version.
I opened a new project in the cloned folder and retrieving the parallella source from there.

Vivado looks like simulate quite well all the steps (not able to say if any of that warning may be critical)

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(13) - Only lower order bits will be connected.

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(13) - Only lower order bits will be connected.

WARNING: [Runs 36-53] Possible issues detected after target generation. Generation state is unexpected for target 'Simulation'. Expected 'Generated', got 'Stale' for source '/home/user /parallella/parallella-fpga/adexparallella/adexparallella.srcs/sources_1/bd/base_zynq/base_zynq.bd'

This was the 3 ones marked in red that may provide some hint for some critical issues.

I ask here but please reply in post Can anyone point me in whitch part the "gpu/bitstraem" already in use is described/implemented ?

Thanks

Statistics: Posted by adexmont — Sun Aug 06, 2017 1:12 pm

]]> 2017-06-23T16:09:59+00:00 2017-06-23T16:09:59+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19327#p19327 <![CDATA[Re: Isn't there any board file for Parallella to use in Viva]]> Statistics: Posted by svartalf — Fri Jun 23, 2017 4:09 pm

]]> 2017-05-19T14:01:20+00:00 2017-05-19T14:01:20+00:00 https://parallella.org/forums/viewtopic.php?t=4068&p=19063#p19063 <![CDATA[Isn't there any board file for Parallella to use in Vivado?]]> I mean add Parallella board to this dialogue:

Statistics: Posted by parallella-project — Fri May 19, 2017 2:01 pm

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