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Parallella Community Supercomputing for Everyone 2015-09-21T12:30:25+00:00 https://parallella.org/forums/feed.php?f=9&t=3206 2015-09-21T12:30:25+00:00 2015-09-21T12:30:25+00:00 https://parallella.org/forums/viewtopic.php?t=3206&p=15871#p15871 <![CDATA[Re: 8Gbps low latency chip to chip]]> Statistics: Posted by sebraa — Mon Sep 21, 2015 12:30 pm

]]> 2015-09-20T22:58:38+00:00 2015-09-20T22:58:38+00:00 https://parallella.org/forums/viewtopic.php?t=3206&p=15870#p15870 <![CDATA[8Gbps low latency chip to chip]]>
I surfingly came accross this blog post about a fast interface:



I"ve looked at it a bit and saw there is a simulation and so on, but is it possible to try to use this interface with the 7010 board in practice ? Or would it require supercooling ?! :)

I mean I've not gone over all the memory mapped control fields to see if they are simular to the standard IF or looked at the verlog interface code to see if there are implementation parts there for the Zynq at hand, but it would be very nice if such speed (like suggested when the project started) would be available to work with a bit !

Theo V.

Statistics: Posted by theover — Sun Sep 20, 2015 10:58 pm

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