Parallella Community

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	Zynq docoumentation by aolofsson » Thu Apr 17, 2014 3:26 pm	Replies: 0 Views: 46851	Thu Apr 17, 2014 3:26 pm by aolofsson

Statistics	Last post
Figuring out where addresses comes from? by mkaczanowski » Mon Feb 17, 2020 8:47 pm	Replies: 1 Views: 79451	Sat Mar 28, 2020 1:45 pm by mkaczanowski
Generate bitstream with Vivado 2019.x by mkaczanowski » Mon Feb 10, 2020 10:31 pm	Replies: 2 Views: 18682	Mon Feb 17, 2020 8:13 pm by mkaczanowski
Vivado(_hls) 2019.2 , Anyone ? by theover » Sat Dec 07, 2019 12:25 pm	Replies: 7 Views: 34935	Wed Jan 08, 2020 5:16 pm by theover
creating a output register/interrup from PL to arm processor 1, 2 by dipin » Tue May 29, 2018 12:30 pm	Replies: 11 Views: 88007	Wed Nov 07, 2018 12:01 am by cpantel
how to add push button to GPIO? by parallella-project » Mon Aug 13, 2018 1:39 pm	Replies: 2 Views: 24280	Fri Aug 17, 2018 1:57 am by olajep
no device detected using jtag by parallella-project » Thu May 31, 2018 11:32 am	Replies: 1 Views: 20747	Fri Jun 08, 2018 2:15 pm by olajep
Synthesis Error:loop statement with empty body is not permit by Min » Sat Jun 02, 2018 1:33 am	Replies: 1 Views: 20574	Wed Jun 06, 2018 5:25 am by dipin
error after make command to build a vivado project by parallella-project » Mon May 28, 2018 5:39 am	Replies: 6 Views: 38930	Tue Jun 05, 2018 5:18 pm by Min
parallella desktop edition: fpga to arm processor interrupt by dipin » Tue Jun 05, 2018 5:20 am	Replies: 1 Views: 20424	Tue Jun 05, 2018 5:01 pm by Min
how to install uio drivers in parallella board by dipin » Thu May 10, 2018 1:47 pm	Replies: 1 Views: 21266	Sun May 20, 2018 6:42 am by Min
using headless kernal in parallella fpga with an hdmi by dipin » Wed May 16, 2018 5:46 am	Replies: 2 Views: 23140	Thu May 17, 2018 10:03 am by olajep
Xilinx Design Constraint by parallella-project » Wed May 16, 2018 4:16 pm	Replies: 1 Views: 20207	Thu May 17, 2018 9:17 am by olajep
where has parallella vivado project been moved in github? by parallella-project » Wed Mar 07, 2018 3:39 pm	Replies: 3 Views: 30953	Thu Mar 29, 2018 6:16 am by Min
Open source GPU by minkanjin » Sat Jun 04, 2016 7:39 pm	Replies: 3 Views: 32284	Mon Sep 25, 2017 3:46 pm by adexmont
FPGA Accelerator by promach » Tue Jan 03, 2017 7:47 am	Replies: 5 Views: 49874	Tue Sep 05, 2017 3:20 pm by olajep
Isn't there any board file for Parallella to use in Vivado? by parallella-project » Fri May 19, 2017 2:01 pm	Replies: 7 Views: 49018	Wed Aug 16, 2017 10:43 pm by frankbuss
github asicguy gplgpu --> FPGA 7020 by adexmont » Sat Aug 05, 2017 9:38 am	Replies: 1 Views: 22588	Mon Aug 14, 2017 5:27 pm by sebraa
Troubles rebuilding the FPGA by avignani » Fri Sep 16, 2016 11:20 pm	Replies: 5 Views: 37352	Wed Aug 09, 2017 4:36 pm by frankbuss
PL fabric clock by a_k » Wed Feb 17, 2016 9:52 am	Replies: 8 Views: 53825	Sat Aug 05, 2017 4:43 pm by MelHance
Why does Oh! Library AXI convert between eMesh and Packets by ninlar » Wed Jun 21, 2017 11:57 pm	Replies: 9 Views: 53439	Fri Jun 30, 2017 2:05 pm by olajep
Cannot boot after adding FPGA accelerator 1, 2 by jimmystone » Sun May 21, 2017 9:14 am	Replies: 10 Views: 65242	Thu Jun 22, 2017 3:14 pm by sebraa
risc-v and such by jlambrecht » Sun Jun 05, 2016 7:42 pm	Replies: 7 Views: 45403	Thu May 25, 2017 3:12 pm by promach
Timing violation of Parallella PFGA project by jimmystone » Sun May 21, 2017 8:58 am	Replies: 0 Views: 20565	Sun May 21, 2017 8:58 am by jimmystone
LEON3 CPU - FPGA by bgeorge » Tue Apr 18, 2017 12:33 pm	Replies: 2 Views: 24349	Wed Apr 19, 2017 11:19 am by bgeorge
When using EMIO do I need to rebuild the FSBL by wiegmink » Thu Mar 30, 2017 1:31 pm	Replies: 2 Views: 24312	Sat Apr 01, 2017 1:48 pm by olajep

Topics

Statistics

Last post

Figuring out where addresses comes from?

by mkaczanowski » Mon Feb 17, 2020 8:47 pm

Replies: 1

Views: 79451

Sat Mar 28, 2020 1:45 pm

by mkaczanowski

Generate bitstream with Vivado 2019.x

by mkaczanowski » Mon Feb 10, 2020 10:31 pm

Replies: 2

Views: 18682

Mon Feb 17, 2020 8:13 pm

by mkaczanowski

Vivado(_hls) 2019.2 , Anyone ?

by theover » Sat Dec 07, 2019 12:25 pm

Replies: 7

Views: 34935

Wed Jan 08, 2020 5:16 pm

by theover

creating a output register/interrup from PL to arm processor

1, 2

by dipin » Tue May 29, 2018 12:30 pm

Replies: 11

Views: 88007

Wed Nov 07, 2018 12:01 am

by cpantel

how to add push button to GPIO?

by parallella-project » Mon Aug 13, 2018 1:39 pm

Replies: 2

Views: 24280

Fri Aug 17, 2018 1:57 am

by olajep

no device detected using jtag

by parallella-project » Thu May 31, 2018 11:32 am

Replies: 1

Views: 20747

Fri Jun 08, 2018 2:15 pm

by olajep

Synthesis Error:loop statement with empty body is not permit

by Min » Sat Jun 02, 2018 1:33 am

Replies: 1

Views: 20574

Wed Jun 06, 2018 5:25 am

by dipin

error after make command to build a vivado project

by parallella-project » Mon May 28, 2018 5:39 am

Replies: 6

Views: 38930

Tue Jun 05, 2018 5:18 pm

by Min

parallella desktop edition: fpga to arm processor interrupt

by dipin » Tue Jun 05, 2018 5:20 am

Replies: 1

Views: 20424

Tue Jun 05, 2018 5:01 pm

by Min

how to install uio drivers in parallella board

by dipin » Thu May 10, 2018 1:47 pm

Replies: 1

Views: 21266

Sun May 20, 2018 6:42 am

by Min

using headless kernal in parallella fpga with an hdmi

by dipin » Wed May 16, 2018 5:46 am

Replies: 2

Views: 23140

Thu May 17, 2018 10:03 am

by olajep

Xilinx Design Constraint

by parallella-project » Wed May 16, 2018 4:16 pm

Replies: 1

Views: 20207

Thu May 17, 2018 9:17 am

by olajep

where has parallella vivado project been moved in github?

by parallella-project » Wed Mar 07, 2018 3:39 pm

Replies: 3

Views: 30953

Thu Mar 29, 2018 6:16 am

by Min

Open source GPU

by minkanjin » Sat Jun 04, 2016 7:39 pm

Replies: 3

Views: 32284

Mon Sep 25, 2017 3:46 pm

by adexmont

FPGA Accelerator

by promach » Tue Jan 03, 2017 7:47 am

Replies: 5

Views: 49874

Tue Sep 05, 2017 3:20 pm

by olajep

Isn't there any board file for Parallella to use in Vivado?

by parallella-project » Fri May 19, 2017 2:01 pm

Replies: 7

Views: 49018

Wed Aug 16, 2017 10:43 pm

by frankbuss

github asicguy gplgpu --> FPGA 7020

by adexmont » Sat Aug 05, 2017 9:38 am

Replies: 1

Views: 22588

Mon Aug 14, 2017 5:27 pm

by sebraa

Troubles rebuilding the FPGA

by avignani » Fri Sep 16, 2016 11:20 pm

Replies: 5

Views: 37352

Wed Aug 09, 2017 4:36 pm

by frankbuss

PL fabric clock

by a_k » Wed Feb 17, 2016 9:52 am

Replies: 8

Views: 53825

Sat Aug 05, 2017 4:43 pm

by MelHance

Why does Oh! Library AXI convert between eMesh and Packets

by ninlar » Wed Jun 21, 2017 11:57 pm

Replies: 9

Views: 53439

Fri Jun 30, 2017 2:05 pm

by olajep

Cannot boot after adding FPGA accelerator

1, 2

by jimmystone » Sun May 21, 2017 9:14 am

Replies: 10

Views: 65242

Thu Jun 22, 2017 3:14 pm

by sebraa

risc-v and such

by jlambrecht » Sun Jun 05, 2016 7:42 pm

Replies: 7

Views: 45403

Thu May 25, 2017 3:12 pm

by promach

Timing violation of Parallella PFGA project

by jimmystone » Sun May 21, 2017 8:58 am

Replies: 0

Views: 20565

Sun May 21, 2017 8:58 am

by jimmystone

LEON3 CPU - FPGA

by bgeorge » Tue Apr 18, 2017 12:33 pm

Replies: 2

Views: 24349

Wed Apr 19, 2017 11:19 am

by bgeorge

When using EMIO do I need to rebuild the FSBL

by wiegmink » Thu Mar 30, 2017 1:31 pm

Replies: 2

Views: 24312

Sat Apr 01, 2017 1:48 pm

by olajep

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FPGA Design

Zynq docoumentation

Figuring out where addresses comes from?

Generate bitstream with Vivado 2019.x

Vivado(_hls) 2019.2 , Anyone ?

creating a output register/interrup from PL to arm processor

how to add push button to GPIO?

no device detected using jtag

Synthesis Error:loop statement with empty body is not permit

error after make command to build a vivado project

parallella desktop edition: fpga to arm processor interrupt

how to install uio drivers in parallella board

using headless kernal in parallella fpga with an hdmi

Xilinx Design Constraint

where has parallella vivado project been moved in github?

Open source GPU

FPGA Accelerator

Isn't there any board file for Parallella to use in Vivado?

github asicguy gplgpu --> FPGA 7020

Troubles rebuilding the FPGA

PL fabric clock

Why does Oh! Library AXI convert between eMesh and Packets

Cannot boot after adding FPGA accelerator

risc-v and such

Timing violation of Parallella PFGA project

LEON3 CPU - FPGA

When using EMIO do I need to rebuild the FSBL

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