Parallella Community

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	Zynq docoumentation by aolofsson » Thu Apr 17, 2014 3:26 pm	Replies: 0 Views: 18031	Thu Apr 17, 2014 3:26 pm by aolofsson

Statistics	Last post
Audio playback 1 ... 6, 7, 8 by patc » Fri Sep 19, 2014 10:35 pm	Replies: 78 Views: 174570	Wed Mar 01, 2017 10:37 am by patc
sd card emulation by e97 » Wed Jan 25, 2017 7:50 am	Replies: 0 Views: 6342	Wed Jan 25, 2017 7:50 am by e97
How to set_property for my IP in oh by jimmystone » Mon Dec 26, 2016 2:08 pm	Replies: 0 Views: 6793	Mon Dec 26, 2016 2:08 pm by jimmystone
Elink Project by blahbidy » Fri Nov 04, 2016 9:41 pm	Replies: 0 Views: 5015	Fri Nov 04, 2016 9:41 pm by blahbidy
Example DMA design (Vivado 2015.4) 1, 2 by kirill » Sat Jan 30, 2016 7:40 am	Replies: 11 Views: 31533	Sun Oct 02, 2016 1:33 am by theover
Vivado HLx 2016.1 C to FPGA by theover » Thu May 19, 2016 8:59 pm	Replies: 3 Views: 8987	Fri Sep 02, 2016 9:17 am by theover
Vivido project for parallella by jimmystone » Fri Aug 12, 2016 9:26 am	Replies: 5 Views: 12815	Tue Aug 16, 2016 12:09 pm by jimmystone
How about computing a cosine in FPGA by theover » Tue Jun 14, 2016 2:30 pm	Replies: 3 Views: 14117	Tue Aug 09, 2016 3:52 pm by NeilKeiding
Xilinx Webpack 2015.4 HLx edition by theover » Tue Dec 29, 2015 1:52 pm	Replies: 8 Views: 20454	Tue May 31, 2016 11:00 am by theover
FPGA access in Linux 4.4 1, 2 by sebraa » Fri May 06, 2016 2:51 pm	Replies: 11 Views: 27320	Sat May 14, 2016 10:08 am by kirill
eLink FPGA project 1, 2 by Riwa » Fri May 15, 2015 7:37 am	Replies: 12 Views: 29874	Sat Jan 30, 2016 10:32 pm by peteasa
Minimal Vivado Project 2015.3 1, 2 by kirill » Sat Nov 14, 2015 1:12 pm	Replies: 16 Views: 41975	Wed Jan 20, 2016 8:34 am by kirill
Changing Voltage on PS SPI when routed to EMIO by Kalicutt » Thu Jan 07, 2016 3:13 pm	Replies: 1 Views: 5423	Fri Jan 08, 2016 2:04 pm by Kalicutt
Enabling Voltage Level Shifters between PS-PL by Kalicutt » Tue Dec 29, 2015 3:12 pm	Replies: 1 Views: 6075	Thu Jan 07, 2016 3:19 pm by Kalicutt
OH. by peteasa » Sat Oct 24, 2015 7:47 pm	Replies: 4 Views: 10017	Mon Nov 30, 2015 10:39 pm by peteasa
First step with parallella 1, 2 by zodane » Fri Feb 13, 2015 10:56 am	Replies: 15 Views: 26190	Thu Nov 26, 2015 9:00 pm by peteasa
FPGA Programming by mabdinur85 » Sat Nov 21, 2015 9:23 am	Replies: 2 Views: 7229	Tue Nov 24, 2015 11:46 am by mabdinur85
Working with Vivado by theover » Wed Nov 18, 2015 6:58 pm	Replies: 0 Views: 4219	Wed Nov 18, 2015 6:58 pm by theover
Reloading elink by frodo » Mon Oct 26, 2015 9:29 pm	Replies: 5 Views: 9954	Sun Nov 15, 2015 7:48 am by kirill
How about some simple FPGA example "programs" by theover » Sat Oct 24, 2015 4:56 pm	Replies: 4 Views: 8758	Sun Nov 15, 2015 7:39 am by kirill
Vivado project for 7010 headless by kirill » Tue Sep 29, 2015 11:50 am	Replies: 6 Views: 12157	Thu Oct 22, 2015 10:34 am by kirill
IOSTANDARD conflict by a_k » Wed Oct 21, 2015 2:12 pm	Replies: 0 Views: 5051	Wed Oct 21, 2015 2:12 pm by a_k
Using M_AXI_GP0 of PS [Solved] by a_k » Fri Oct 09, 2015 12:47 pm	Replies: 2 Views: 6075	Wed Oct 21, 2015 7:40 am by a_k
FPGA questions by Riwa » Sun Oct 04, 2015 12:39 pm	Replies: 1 Views: 4830	Sat Oct 17, 2015 4:37 am by kirill
Parallella FPGA Tutorials available 1, 2, 3, 4, 5 by yanidubin » Tue Sep 23, 2014 7:55 am	Replies: 49 Views: 95574	Tue Oct 13, 2015 1:58 am by tif

Topics

Statistics

Last post

Audio playback

1 ... 6, 7, 8

by patc » Fri Sep 19, 2014 10:35 pm

Replies: 78

Views: 174570

Wed Mar 01, 2017 10:37 am

by patc

sd card emulation

by e97 » Wed Jan 25, 2017 7:50 am

Replies: 0

Views: 6342

Wed Jan 25, 2017 7:50 am

by e97

How to set_property for my IP in oh

by jimmystone » Mon Dec 26, 2016 2:08 pm

Replies: 0

Views: 6793

Mon Dec 26, 2016 2:08 pm

by jimmystone

Elink Project

by blahbidy » Fri Nov 04, 2016 9:41 pm

Replies: 0

Views: 5015

Fri Nov 04, 2016 9:41 pm

by blahbidy

Example DMA design (Vivado 2015.4)

1, 2

by kirill » Sat Jan 30, 2016 7:40 am

Replies: 11

Views: 31533

Sun Oct 02, 2016 1:33 am

by theover

Vivado HLx 2016.1 C to FPGA

by theover » Thu May 19, 2016 8:59 pm

Replies: 3

Views: 8987

Fri Sep 02, 2016 9:17 am

by theover

Vivido project for parallella

by jimmystone » Fri Aug 12, 2016 9:26 am

Replies: 5

Views: 12815

Tue Aug 16, 2016 12:09 pm

by jimmystone

How about computing a cosine in FPGA

by theover » Tue Jun 14, 2016 2:30 pm

Replies: 3

Views: 14117

Tue Aug 09, 2016 3:52 pm

by NeilKeiding

Xilinx Webpack 2015.4 HLx edition

by theover » Tue Dec 29, 2015 1:52 pm

Replies: 8

Views: 20454

Tue May 31, 2016 11:00 am

by theover

FPGA access in Linux 4.4

1, 2

by sebraa » Fri May 06, 2016 2:51 pm

Replies: 11

Views: 27320

Sat May 14, 2016 10:08 am

by kirill

eLink FPGA project

1, 2

by Riwa » Fri May 15, 2015 7:37 am

Replies: 12

Views: 29874

Sat Jan 30, 2016 10:32 pm

by peteasa

Minimal Vivado Project 2015.3

1, 2

by kirill » Sat Nov 14, 2015 1:12 pm

Replies: 16

Views: 41975

Wed Jan 20, 2016 8:34 am

by kirill

Changing Voltage on PS SPI when routed to EMIO

by Kalicutt » Thu Jan 07, 2016 3:13 pm

Replies: 1

Views: 5423

Fri Jan 08, 2016 2:04 pm

by Kalicutt

Enabling Voltage Level Shifters between PS-PL

by Kalicutt » Tue Dec 29, 2015 3:12 pm

Replies: 1

Views: 6075

Thu Jan 07, 2016 3:19 pm

by Kalicutt

OH.

by peteasa » Sat Oct 24, 2015 7:47 pm

Replies: 4

Views: 10017

Mon Nov 30, 2015 10:39 pm

by peteasa

First step with parallella

1, 2

by zodane » Fri Feb 13, 2015 10:56 am

Replies: 15

Views: 26190

Thu Nov 26, 2015 9:00 pm

by peteasa

FPGA Programming

by mabdinur85 » Sat Nov 21, 2015 9:23 am

Replies: 2

Views: 7229

Tue Nov 24, 2015 11:46 am

by mabdinur85

Working with Vivado

by theover » Wed Nov 18, 2015 6:58 pm

Replies: 0

Views: 4219

Wed Nov 18, 2015 6:58 pm

by theover

Reloading elink

by frodo » Mon Oct 26, 2015 9:29 pm

Replies: 5

Views: 9954

Sun Nov 15, 2015 7:48 am

by kirill

How about some simple FPGA example "programs"

by theover » Sat Oct 24, 2015 4:56 pm

Replies: 4

Views: 8758

Sun Nov 15, 2015 7:39 am

by kirill

Vivado project for 7010 headless

by kirill » Tue Sep 29, 2015 11:50 am

Replies: 6

Views: 12157

Thu Oct 22, 2015 10:34 am

by kirill

IOSTANDARD conflict

by a_k » Wed Oct 21, 2015 2:12 pm

Replies: 0

Views: 5051

Wed Oct 21, 2015 2:12 pm

by a_k

Using M_AXI_GP0 of PS [Solved]

by a_k » Fri Oct 09, 2015 12:47 pm

Replies: 2

Views: 6075

Wed Oct 21, 2015 7:40 am

by a_k

FPGA questions

by Riwa » Sun Oct 04, 2015 12:39 pm

Replies: 1

Views: 4830

Sat Oct 17, 2015 4:37 am

by kirill

Parallella FPGA Tutorials available

1, 2, 3, 4, 5

by yanidubin » Tue Sep 23, 2014 7:55 am

Replies: 49

Views: 95574

Tue Oct 13, 2015 1:58 am

by tif

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FPGA Design

Zynq docoumentation

Audio playback

sd card emulation

How to set_property for my IP in oh

Elink Project

Example DMA design (Vivado 2015.4)

Vivado HLx 2016.1 C to FPGA

Vivido project for parallella

How about computing a cosine in FPGA

Xilinx Webpack 2015.4 HLx edition

FPGA access in Linux 4.4

eLink FPGA project

Minimal Vivado Project 2015.3

Changing Voltage on PS SPI when routed to EMIO

Enabling Voltage Level Shifters between PS-PL

OH.

First step with parallella

FPGA Programming

Working with Vivado

Reloading elink

How about some simple FPGA example "programs"

Vivado project for 7010 headless

IOSTANDARD conflict

Using M_AXI_GP0 of PS [Solved]

FPGA questions

Parallella FPGA Tutorials available

Who is online

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