Using HW SPI ?

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Using HW SPI ?

Postby tnt » Thu Jun 20, 2013 8:14 am

Hi,

I'm trying to get the hardware SPI working to communicate with an external device (SDR frontend) and somehow doesn't seem to work. (on the zedboard + epiphany)

1) I rebuilt the bitstream following the reference design guide. In addition I also enabled SPI1 and put it on some free MIO pins that are available on pin headers.
2) I rebuilt a kernel and made sure the SPI driver was enabled and that 'spi_dev' was enabled as well so I could access it from userspace
3) I edited the device tree and added an entry for the spi controller and a spi device binding to spi_dev.
4) Rebuilt a SD card boot partition using all of those (I used the previous files for u-boot and the fsbl)

It boots, I can see the spi driver is loaded and bound to the right address for SPI1 0xe0007000 and IRQ 81.
The spidev module also loads properly and creates /dev/spi1.0

However as soon as I try to make an actual transfer, the userspace program just freezes, waiting for an IOCTL that never returns.

Cheers,

Sylvain
tnt
 
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Re: Using HW SPI ?

Postby ticso » Thu Jun 20, 2013 10:43 am

There is also an interrupt mask register in ARM controllers.
In some board implementations they are sparsely enabled and needs to be tuned when adding drivers
In other cases they are just fully enabled, so it just works by attaching drivers and setup io-pin.
Don't know how it is done with uboot and Linux, but from what I've heared I would assume it has to be handled in uboot.
ticso
 
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Re: Using HW SPI ?

Postby tnt » Thu Jun 20, 2013 7:46 pm

I found one issue: you need to regenerate the FSBL since it's what will configure the MIO.
So now at least the SPI pins are no longer controllable from the GPIO driver, that's progress.

But it still doesn't work, so must be another issue ...
tnt
 
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Re: Using HW SPI ?

Postby tnt » Thu Jun 20, 2013 9:37 pm

Ok, I think I found the issues (rebuilding now to confirm).

1) You need to rebuild the FSBL if you change the peripheral config because it's that part which configures MIO and which things are enabled or not

2) SPI is just so darn complicated that Xilinx managed to screw it up : http://www.xilinx.com/support/answers/47511.htm
So don't use SS[0] ... use SS[1].
tnt
 
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