Peak Zynq Freq. reported in parallella ref. manual

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Peak Zynq Freq. reported in parallella ref. manual

Postby ali8 » Wed Jul 10, 2013 5:24 am

Hello,

In the "parallella gen1 reference", page 38, it is stated that Peak Zynq Frequency is 667 MHz.

The Zynq device used in parallella is XC7Z020-1CLG400C, so this is a -1 speed grade device, the slowest available (yes, I know that some -1 devices can actually operate at -2 or even -3 speed grades, but that is not guaranteed, Xilinx guarantee a -1 device to work at only -1 speed grades).

According to "Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics", page 36: CLB Switching Characteristics, we see that for speed grade -1, the slowest switching time in Table 57 is 1.27 ns which gives a max. freq. of 787.4 MHz. (I do know that different components in the FPGA operate at different freq., e.g. the DSP slices have a max. freq. of 464 MHz, but that's not the point).

The ARM processor operate at 667 MHz.

So it seems that we are operating both the FPGA's and the ARM processors at the same freq. even though the FPGA can reach higher freq., right? (by "FPGA", I am at least referring to the CLB and not to the I/O, DSP Slices, etc, although I know that this is practically not useful).

ali8
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Re: Peak Zynq Freq. reported in parallella ref. manual

Postby hamster » Wed Jul 10, 2013 8:44 pm

Nope.

The switching frequency for a Logic block is how quickly an input signal is acted on and becomes a stable output signal. On top of this you have to allow the time for routing the signals between logic blocks, that you may have more than one block between the source and target registers, and allow for clock skews and so on.

As a concrete example, I've made a fractal view that runs on a Zedboard (Zynq-7020) using just the programmable logic. It uses the FPGA's multipliers a lot. Although the multipliers are rated at about 490MHz on the datasheet the static timing for my design is 280MHz (although that isn't bad for using about 60 multipliers).

On this class of FPGA routing delays usually dominate a designs Fmax.
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Re: Peak Zynq Freq. reported in parallella ref. manual

Postby ali8 » Thu Jul 11, 2013 3:40 am

Oh I see, so I was neglecting how the signal comes in the first place to the CLBs...

Yes, we need to look at the minimum value since it will be the bottle nick...

Thank you.
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Re: Peak Zynq Freq. reported in parallella ref. manual

Postby tnt » Thu Jul 11, 2013 6:08 am

There is no "minimum" values. You could make a design that can only run at 1 MHz if you wanted to ...

It's up to you to make your FPGA design properly to reach the frequency you target and only the Xilinx tools will be able to tell you if it met your objectives or not after syntesis and implementation ...
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Re: Peak Zynq Freq. reported in parallella ref. manual

Postby hamster » Thu Jul 11, 2013 9:51 am

It just occurred to me that some people here will not have seen an FPGA timing report... Here is an example of the critical path in one of my designs. The signal comes out of the logic block at X14Y69, and then flows through a few logic blocks ending up at logic block at X12Y74.

Code: Select all
     SLICE_X14Y69.B2      net (fanout=2)        0.644
     SLICE_X14Y69.BMUX    Tilo                  0.261   
     SLICE_X14Y69.C5      net (fanout=2)        0.380   
     SLICE_X14Y69.COUT    Topcyc                0.277   
     SLICE_X14Y70.CIN     net (fanout=1)        0.003   
     SLICE_X14Y70.AQ      Tito_logic            0.611   
     SLICE_X12Y72.A3      net (fanout=1)        0.694   
     SLICE_X12Y72.AMUX    Tilo                  0.251   
     SLICE_X12Y72.BX      net (fanout=2)        1.049   
     SLICE_X12Y72.COUT    Tbxcy                 0.157   
     SLICE_X12Y73.CIN     net (fanout=1)        0.003
     SLICE_X12Y73.COUT    Tbyp                  0.076   
     SLICE_X12Y74.CIN     net (fanout=1)        0.003   
     SLICE_X12Y74.CLK     Tcinck                0.341
     -------------------------------------------------  ---------------------------
     Total                                      5.158ns (2.382ns logic, 2.776ns route)
                                                        (46.2% logic, 53.8% route)


For this FPGA device and speed grade it is guaranteed to take less than 5.158ns, so the design will run at up to about 193 MHz. The names like "Tbxcy" are things like the time it takes the 'bx' input to propagate through to the 'cy' output. Over half the time is required to route the signals between logic blocks, and only 46% is due to the speed of the logic blocks themselves.

It is really annoying when a design fails timing by just a fraction of a nanosecond...
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Re: Peak Zynq Freq. reported in parallella ref. manual

Postby ali8 » Thu Jul 11, 2013 5:11 pm

@hamster

Thanks for that example.
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