JTAG interface

[ESI]

The most urgent thing I need, is a JTAG interface.
I have some samples of the samtec connector, so I decided to use one to connect JTAG.
I designed a small pcb, only covering the PEC-Power.
please have a look and tell me if something could be improved. (eagle files attached)

some explanation:
I will solder the pcb by hand (samtec connect probably under microscope) So I enlarge the smd-pad for the samtec connector for better soldering.
The Xilinx connector is not tested in size right now. The resisitors are 0805 and the pads are big enough to solder by hand.

[tnt]

[ESI]

Hi,
1.
I am having some irregularities with USB as many others do. To look deeper into that matter, I want to look at the EHCI-registers, with JTAG and SDK you can easily do that without disturbing the kernel. I know /dev/mem and mmap would also be an alternative.
2.
I do not trust the FSBL build with Planahead 14.4, so I am going to rebuild the FSBL with 14.7, which I trust more. During my job I also use Zynq, and in 14.7. many things (e.g. wrong PLL settings) have been fixed. Changing the FSBL means flashing the QSPI, means a chance to brick, means I need JTAG to unbrick eventually.
3. I need to change some setting within the FSBL, so same reason, I want the security, that I can unbrick my parallella.

OT: For the USB, I am also planning a Kernel update to the branch master_next of the Xilinx-branch. In another Zynq-based project this fixed eMMC without changing eMMC-driver, so something else, maybe clock, was broken in elder version... just a try.

[ESI]

I guess, I need to correct me the latest Planahead files are from 14.7...

[FHuettig]

[ESI]

Hi there,
JTAG works now, so no excuses for me not to start debugging, updating etc...
see attached pictures.
My test was:
>xmd
XMD> connect arm hw

then I saw the two taps of zynq...
and was happy for ever after....