Interfacing with Host

[hex]

Hi guys!

I understand that there aren't any options for interfacing Parallella directly from a host running arbitrary OS, but I wanted to start a post here to determine what the fastest interconnect could be between Parallella devices as well as between a Parallella device and an arbitrary host (e.g. network controlled, special I/O pins, etc.).

Please specify what interconnects there are available as well as their gross bandwidth (e.g. 1Gb/s ethernet).

Thanks!

[Folknology]

Although I cannot answer your question directly, let me provide some information that may help.

First I am assuming that we are referring to the forthcoming Parallella Boards with the the on board Epiphany chip awarded to those who took part in the Kickstarter project as well as others who may later also purchase the development boards (If you are talking about designing your own boards there are more choices but similar limitations). First I do not have the circuit diagrams and exact components but I do have a general idea of the way the board has been designed.

The Epiphany chips have high bandwidth differential interconnects that allow them to be connected to either other Epiphany chips, FPGAs or combinations of those. Parallella have IP around the HDL of those interconnects that can be implemented in both small and large scale FPGAs depending on how a given board is designed. In the forthcoming boards the Epiphany chip is connected to a Zynq FPGA chip which also has onboard ARM cores. Inside that FPGA will be HDL for both the Epiphany interconnect as well as basic Memory and IO functionality (details of which have yet to be published). Thus if you are talking about connecting to this using say a daughter card you would in fact be interfacing with the FPGA fabric itself. As I understand it you will also be able to configure/reconfigure this at more than one level (remember some of the HDL needs to remain in place for basic operation), thus there will be significant options for interconnect depending on your usage scenario, but any bandwidth used by ones IO connections must fit into any existing bandwidth between the Epiphany, the memory map and any on board peripherals (which will probably include 1Gb/s ethernet as well as USB etc..). In terms of bandwidth between the Epiphany and the Zynq, I believe there is up to 8GB/s via the interconnects but clearly that is being shared as highlighted above, so you will likely be taking a share of that. The key here is that you are not directly interfacing to the Epiphany chip itself, rather you are operating through layers of FPGA HDL via Epiphany interconnects.

Hope this provides some information in the interim and gives an idea of the architecture we will be interfacing with, maybe there will be more documentation forthcoming soon with regard to the actual boards themselves.

regards
Al

[aolofsson]

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