Ideas for daughter cards?

[9600]

[timpart]

I think the E16 only supports grid style topologies as it doesn't have the *MESHROUTE registers feature.

The Parallella only provides north and south eLink extension and there are only 16 possible row addresses for the E16 version. So you can't put more than 16 boards in a line, and there is no way to go sideways. With a daughter board like the one shown above, if the boards arrange the chips in a column you could have three of them plus the Parallella.

Alternatively for a bit more cost you could arrange the four epiphanies in a row rather than a column. Then you would have to provide north south connectors for each of them if you want free reigning communications. Plus some way of attaching the ordinary Parallella to one of the connections. You could get 15 * 4 + 1 chips in such an arrangement. A big power supply and board feeds needed too, doubt you could feed that much current through the Parallella board! The Parallella would only be able to directly talk to one column of chips

Tim

[9600]

[shodruk]

Thanks Tim, Andrew,
I understand that my design has many problems.
I'll reconsider it.

[mhonman]

[shodruk]

Thanks mhonman,
Yes, this is like a puzzle game.
I don't know whether it is possible, I thought of one more eLink topology.

elink01.png (33.34 KiB) Viewed 33909 times

The "Glue board" is for figuring out the physical layout problem.
I think the Epiphanies on the add-on boards and the Zynq can communicate with each other,
but the Epiphany on the Parallella board cannot communicate with add-on boards directly.

Is it possible to implement a eLink using GPIO port?
What problems are there with this idea?

[mhonman]

Not being a hardware guy, I don't know whether the GPIO could be used as another eLink, but it's a very good idea! If so, the "new" link could also be an East or West link.

The advantage of the Zynq being on an east-west e-Link is that its RAM can be exposed as a contiguous address range in Epiphany address space (that was the "lightbulb moment" that struck me in reading Tim's post).

The other really useful bit of info is the relative cost of Epiphany chips and the connectors needed for the high-speed eLink signals - IIRC 3 or 4 of those connectors cost the same as a 16-core Epiphany.

So I think the goal for Parallella expansion should be very limited and always with "hobbyist" pricing in mind.

For parallel-processing expansion it would have been nice for the Parallella's two exposed eLinks to be N and W - then the on-board Epiphany could occupy the SE corner of an arbitrarily-sized matrix of Epiphanies. Such a system couldn't have multiple Parallellas in it, to do that one would need connectors carrying the N, S, and W links.

A recent attack of megalomania prompted the idea of "Parallella Plus", being a bigger Zynq (484 or 485 pin package) with 3 links into the East edge of a 3x3 matrix of Epiphanies - all on one board. But I guess that would be too expensive for anyone to buy just to have a play.

Mark

[9600]

[timpart]

[aolofsson]

There is no problem in creating a second eLink in the FPGA logic and connecting it to the North/South links (or directly to other FPGAs!). In fact this was always part of our "master plan"
More on this soon..