Parallella Community

There are quite a few N/A spaces on the PEC Power connector That I would love to see filled, here are some of the things that would go on my PEC Power wish list:

1) SPI connectors MOSI,MISO,SCLK and at least 1 CEO/SS preferably @ +3v3
2) As many spare Spare GPIOs from the Zync
3) Reset signal pref active low
4) IO +2v5 supply
5) SDIO pref @ +3v3

What would be on your PEC Power wish list to fill the N/As?

Thanks @trioflex you clearly have a lot more insight for the Parellella, is that down to prior Zynq knowledge?

So there may be up to 3 PL lines (depending on assumptions) we could use, would it therefore be possible to use them as Mosi,Miso and Sclk and then we could use CEOs on the FPGA PEC, or would such separation create fragmentation issues forming the SPI HDL inside the Zynq?

regards
Al

Antti, your product is apparently #1, now

Thanks @trioflex I think I have it now which means:

1) If we want SPI on the Power PEC it will be derived from QSPI in 1 bit mode and will need the use of the MIO0 LEDx as a select which we may or may not be able to use (this could be connected to an internal LED in which case were pretty much fried).
2) If it is possible to do above we will loose 1 LEDx, I2C and SPDIF functionality.

Given that there are no more pins we can route to the PEC Power connector generally it does't look good for SPI on Power PEC, in fact I would highly unlikely.

However on the bright side the CAN mapping possibility for Rx/Tx looks handy for adding a CAN transceiver

regards
Al

Al, maybe you need to read section 2.5 of the Zynq technical reference manual (TRM) to get a grasp of how the IOs work.

http://www.xilinx.com/support/documenta ... 00-TRM.pdf

Yeah well I have started with the 1700 page tome