Cache Line Size

Discussion about Parallella (and Epiphany) Software Development

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Cache Line Size

Postby jain.ramya » Sat Aug 08, 2015 1:44 pm

Dear Sir,

I would like to know how I could get d-Cache line size on parallealla cluster.

I tried a simple program
#include <stdio.h>

int main(void) {
unsigned int cache_info = 0;
unsigned int dcache_lsize;

asm volatile("mrc p15, 0, %0, c0, c0, 1":"=r" (cache_info));
dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
printf("dcache line size: %d\n", dcache_lsize);
return 0;
}
but results in illegal instruction, though the ARM ABI says the mrc instruction is supported.

Any help with this would be deeply appreciated.
jain.ramya
 
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Re: Cache Line Size

Postby timpart » Fri Sep 18, 2015 4:49 pm

Are you confusing the ARM processors on the Parallella board FPGA with the 16 Epithany cores?

The Epithany cores are not ARM based, so ARM instructions are not valid on them. To answer your question, the Epithany has no data or instruction cache on it, so there is no line size.

Tim
timpart
 
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Location: UK

Re: Cache Line Size

Postby sebraa » Fri Sep 18, 2015 5:54 pm

Are you sure that you can access this register from userspace?
At least some other registers (i.e. MIDR, TLBTR, MPIDR etc) are only accessible in privileged mode, i.e. not from an application.
sebraa
 
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