Cache Line Size
Posted: Sat Aug 08, 2015 1:44 pm
Dear Sir,
I would like to know how I could get d-Cache line size on parallealla cluster.
I tried a simple program
#include <stdio.h>
int main(void) {
unsigned int cache_info = 0;
unsigned int dcache_lsize;
asm volatile("mrc p15, 0, %0, c0, c0, 1":"=r" (cache_info));
dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
printf("dcache line size: %d\n", dcache_lsize);
return 0;
}
but results in illegal instruction, though the ARM ABI says the mrc instruction is supported.
Any help with this would be deeply appreciated.
I would like to know how I could get d-Cache line size on parallealla cluster.
I tried a simple program
#include <stdio.h>
int main(void) {
unsigned int cache_info = 0;
unsigned int dcache_lsize;
asm volatile("mrc p15, 0, %0, c0, c0, 1":"=r" (cache_info));
dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
printf("dcache line size: %d\n", dcache_lsize);
return 0;
}
but results in illegal instruction, though the ARM ABI says the mrc instruction is supported.
Any help with this would be deeply appreciated.