Parallella 2.0 Design Specifications

[MikeChambers]

Andreas,
I think before I can give meaningful input, I need a clearer idea about where Adapteva is headed as a business and whether the success of Parallella has changed the prior business direction.

As I understood Adapteva's business goal early on, it was to focus on IP licensing of Epiphany for those of us potentially interested in embedding Epiphany in our own silicon. Parallella was a very slick way to get a development platform for Epiphany evaluators way, way down in cost. However, if the success of Parallella has Adapteva considering a move from IP only to IP and system PCB design/manufacturing, that's a different landscape entirely that requires a broader view on product line, entry points, etc. It also has ramifications for types of employees hired, funding strategic vendor partnering, ...

So the $64,000 question is, "What does Adapteva want to be when I grows up?" Is Adapteva an Epiphany company, a Parallella company, both or TBD. I assume that since you recently took Series B funding, those questions have been considered to some degree.

In either case, I'd encourage Adapteva to avoid letting Parallella's success impede further improvement of the Epiphany Architecture (beyond just growing the core count). As valuable as getting feedback on what future generations of a Parallella board should have, I hope you'll be getting feedback from those undertaking analysis and design of Epiphany based/enhanced products. For example, the RISC principle's guiding the architecture are solid for general purpose use; however the type of applications in which Epiphany could have a very substantial impact are double word FP today and moving to quad word soon. The less computationally intensive work that Epiphany passes on, the less relevant it becomes for real world parallel computing needs.

Please don't take the above as criticism. I'm an Epiphany fanboy. With clarification on the business goal, I can gather up some feedback.

Mike.

[twmemphis]

Hi!

One of the reasons for the redesign was the EOL of the DDR3 chip in x32 organization.
I mentioned it in another thread before that there is a fully compatible replacement part available, ready and shipping form Intelligent Memory. 8Gb DDR3, 256Mx32, BGA136, part# IM8G32D3FBBG
Click here for datasheet:

If a new Parallella 2.0 Board uses two 16 Bit wide chips instead, the total memory capacity could get as high as 2 Gigabyte by using two 8Gb DDR3, 512Mx16, BGA96, part # IM8G16D3FBBG
Click here for datasheet:

Both parts are also available in the USA. Just send mail to ussales@memphis.ag (CC to sales@memphis.ag).

Maybe some people would like to have 2GB memory?

[Melkhior]

[xilman]

[zodane]

I wish that Parallella 2.0 come with this features:
1- full support to Vivado, Simulink(Matlab)
2- Zynq 7045 (as a remedy for the surface used for hdmi and elink)
3- Epiphany 64 or 256
4- 1 Giga memory for epiphany (i dont know if it is possible)
5- A better eSDK for the epipihany
maybe the price will be (i'm sure ) but if so, it will be a powerful board

[piotr5]

oh well, completely forgot to store my wishes here. although now it might be too late as the development team hopefully has already finished a first design and is now testing. in that case it's for parallella 3.0...

1) a 3rd eLink, and be it just some pins to solder onto. maybe just connect ssd to this eLink so the client has the choice between ssd card and that 3rd eLink, but not both. (and maybe make ssd accessible from epiphany directly, so the arm has to take the detour through epiphany too.)
2) faster memory-bandwidth from the hardware-side
3) detatchable connector-barrels for power, usb, network and hdmi in the embedded version -- otherwise it isn't really embedded as the connectors are located inside the device and not where they belong. maybe also make ssd detatched and accessible through printed-circuits-cables as found in many laptops. then the device should boot from local flash-memory in case the connection dies.
4) fix the problem with unused usb-power-connector, make it talk to the device from which it gets the power. take a look at in that respect.
5) use a 4-core arm processor, to keep up with the competition.
6) lower fpga temperature.
7) more powerful power-management, add something alike to wake-on-lan but for elink connections. hibernate-to-ram, like laptops usually do.
8) not really for the parallella board, but generally think about the possibility of shadow-ram, move epiphany-memory to the 1GB local memory area and see what happens. same with memory provided by fpga. then describe your findings in the documentation and fix bugs in the next board. we're hitting the 4GB limit, so it's time to look what solutions could possibly circumvent that -- save for going 64-bit. nowadays software relies on >4GB for all the various processing tasks...
9) least and last suggestion I have is to take a look at to reduce production-costs for the downside of getting larger-sized and slower boards. is it possible to somehow create a parallella on paper/carton/solar-panel-glass? of course the challange of attaching micro-chips to such material as of yet...

[manklee]

[quote="Forar"]
... No horizontal clearance. The microhdmi to hdmi plug has a large bend, and that bend doesn't allow me to plug in a microusb slot. So I can either type, or see what's going on unless I want to chance it by barely having the cables in, and this is after I shaved off a large part of the casing.

I have the same problem. I shaved off a large part of the hdmi connector and it was still a very tight fit. Eventually, the USB connector popped right off the board!! Adding some space between all the connectors would help a lot.

[adexmont]

http://www.sciencedaily.com/releases/20 ... 131007.htm
just a dream on how the next epiphany may be.
You are closer than me and as PUP project you may have some useful information about this new technology.
May the future will be able to remove any concept of patent and copyright protection and allow people to get access as deepest as they cares.



Thanks

[piotr5]

I have another idea how 3rd elink can be used while at the same time spreading popularity of epiphany and its eLink protocol: create an open-source chip implementing something alike to nvidia's cuda or whatever other GPU's pixelshader part, while making use of eLink for memory-access and some subset of the assembler language on epiphany for the single-line-multi-processing units. then talk with companies which don't have that kind of hardware in their GPU to fund the development of this chip and help writing PAL drivers for it. if the money-problem is out of the way, you can put this chip on parallella 2.0 or 3.0 as a coprocessor for the epiphany to implement some kind of 3d-acceleration...

nvidia is offering >5TFlops processing power at 150W. I bet you could do better! if the GPUs are then using eLink to communicate with this chip, it shouldn't be difficult to convince them to also talk with epiphany once you equipt it with thousands of cores and some PAL is established standard...

edit: just learned this is old news from last year. MSI N730K-2GD3/OC using the GT 730 is capable of 773 GFlops at 23W thanks to the overclocking. this is in the same GFLOPS range as some 145W card with the mentioned 5TFlops. this card has 33.6, while the best I've seen of the new gtx980 was 34.69 GFlops/W. now if only someone would actually combine lots of pci 2.0 x16 dual slots into a single board with some low-energy processor to scale up those tiny 50$ cards, and add an os support for huge amounts of video cards...

[briaeros007]

What I'd like to the new parallela
- to have power/... on one side, and communication (usb, ethernet, hdmi) on the over side. This way, we can keep things neat, and not a plenty of wire everywhere
- to drop samtec (or at least not populate them for "cost sensitive" version) and put standard arduino-like connector for the FPGA gpio connectors. (could be in any other place and to "solder yourself).
the use of the zynq for a "DIY" is really unoptimized. For example We could use a 8051 in the zyq to get information from multiples sensors/IMU, use the power crunching of the epiphany to establish what you want in fusion algorithm/Neural network decision making etc...
It then will be much more easier to use it in embedded scenario, where it could really shine (I have already plenty possible usage in my mind )
- to add a +5v/gnd (or +12v/gnd) connector for the fan.
- to move the big capacitors to help putting a big heatsink which cover the two die.
- to accept multiples power input from 3v to 15v. When I see that the leaflab mini could do it for less than $4.5, stm32 include, it must be possible for the parallela (but yes, it's not the same draw so not the same cost).
- to keep 1gpbs ethernet
- to keep the serial pins (if no ftdi)
- to have a li-ion battery manager (not sure it will be well used, but could be really useful in some embedded scenario.)

All in one, I also agree that the direction of Adapteva (and the new board) must be definied to have the best ideas of evolution :
If the target is embedded and not desktop
-> the micro-usb , it could do power _and_ serial with a ftdi chip.
-> the hdmi wouldn't be necessary
-> the more "connectivity" , the better : gpio easily accessible, and idea of (and/or compatibility with existing) shields. (gpio with i2c, spi, pwm , 3.3v / 5v compatible, ...)
-> the input voltage tolerance, and multiples power source (usb, battery, directly on specific pin, ...) could also be good points.
-> possibility to easily and cheaply integrate dsp, and/or adc/dac (via gpio ?) in the workflow
For example, in the "parallela SDR" project, there are a $700+ (and certainly more than a thousands) daughter card, without any "big fpga" nor dsp, to analyse in real time 2*2*2*12bits*56Msps (2 way (rx/tx) * 2 channel (mimo) * 2 stream (I and Q) * 12 bits (size of sample) * 56 Msps). I don't think that the zynq 7020 will be enough to do the first filters before the epiphany.