ADCs in the ZYNQ7010

[psupine]

Hi all,

The ZYNQ7010 ARM chip has the resources to implement two ADCs built-in (12bit at 1MHz). The Xilinx doco talks about instantiating the ADCs, and I read that as at least some of the FPGA resouces being needed to implement the ADCs.

Will the FPGA section be locked down to prevent further user changes? If this is the case, will the ADCs be instantiated and will the ADC inputs be part of the Parallella IO header?

[9600]

The FPGA won't be locked down and the HDL source will be provided under an open source licence.

[trioflex]

[aolofsson]

[trioflex]

[psupine]

[aolofsson]

[psupine]

The pinout package document you referenced, refers to the following for the XADC document for further pinout description.



My reading of this (admittedly a single cursory reading) is that there are some dedicated package pins in bank zero with a _0 suffix on the names (Ref, p 13), and External Analog Inputs that are "allocated evenly over banks 15 and 35", with a caveat to consult yet another document to be sure. I did find your "Bank 35 contains the XADC auxiliary inputs" quote so maybe Bank 15 is used on the 7000 series FPGA parts but not the SoC parts.

But in any case the dedicated pins listed in UG865 Table 1-2 (p6), are available without any internal conflict. That is:

VP_0 (K9)
VN_0 (L10)
VREFP_0 (L9)
VREFN_0 (K10)
VCCADC_0 (J9)
GNDADC_0 (J10)

The pinouts are from



assuming you're using the CLG400 package.

How do you feel about putting VP_0 and VN_0 on a header and decoupling the others appropriately? It's going to be a PITA to route

[trioflex]

XADC dedicated pins are in the middle of the die, however they are not so hard to use if you properly fan out the BGA pins so that below BGA there will be middle island and more escape routes.

REF3312 and 4 pin BGA LDO can be placed in the middle, and then you can easily route out VP_P and VP_N. Sure the extra reference and LDO would probably kill the $ budget..

/Antti

[frank_buss]