Parallella Community

Hi,

I was looking at the XPS settings for the HDMI 7010 project. I've successfully "silicon compiled" the exact same .bit file before with my ISE14.7 (linux64), but now I touched on of the entries circled below:



and as it seems the menus might have changed even though i didn't intend to, and there's no general XPS "Cancel" as far as i can see, so now I got a warning about "potentially clashing address spaces" at the end of my "create bit file" run from planAhead, and a different .bit file (different size).

Does anyone know by heart the settings circled above ?

Of course I could redownload the project, but maybe someone knows it from the top of their head.

Also, I was wondering; is it possible to make a whole new setup with XPS for planAhead to use, as in a different DMA structure and kernel bindings ? I mean I have only webpack license, so planAhead makes clear every run it's not licenced, but I recall reading there should be a way to program 7010/20/30s with it, what can it and can it not do ?

Regards,

Theo V.

Nobody interested in this ?

In short, I suppose the different .bit file is because of different git versions of the FPGA source.

I git cloned the latest repo into a new dir, ran the standard procedure, and got a different bit than the standard downloadable too. changing asmall thing in XPS and back, and re-running "gen bitfile " didin't even restart the whole make.

T.