hdmi and clock for EP1G301

[trioflex]

Hi

how is 800MHz clock prepared and what is HDMI controller?

It seems on some pics that HDMI is done FPGA fabric using FPGA TDMS capable pins directly. HDMI in FPGA does burn heat a lot specially at higher resolutions - and so maybe the block in FPGA fabric names "HDMI controller" is not HDMI controller but just an interface to external HDMI transmitter? Similarly to the HDMI transmitter in Zedboard. That would explain the TQFP64 IC on the PCB.

Another puzzle is 800MHz clock that is required - it doesn't look that parallel has clock PLL IC on PCB, so it is assumed the clock is done with Zynq FPGA fabric PLL?

Reading Xilinx datasheets, the maximum clock that can be made available on LVDS pins is 600MHz ?
Of course it may also be possible to generate external 800MHz clock with Zynq, but this is then out of the Xilinx data sheet specifications?

Or have I missed something?

from Xilinx data sheet for zynq:

FMAX_BUFG 628.00 MHz for speed grade -1

this would also be maximal clock that Zynq can generate without violating specs. Where does 800Mhz come for EP1 chip?


Antti

[tnt]

You can see the HDMI transmitter on Figure 1.

[trioflex]

[aolofsson]

@Antti

There is an HDMI transmitter IC on the board that receives 16 bits of data. I am sure you can guess what chip we are working with, but we won't commit to any chip until we have the pricing where we want it. That's why we are also holding off on publishing the schematics openly.(at least for a couple of more weeks).

[trioflex]