Hello,
I have a question regarding some synchronization issues between the ARM cores and the eCores. I know from that the recommended method of synchronization for now is to constantly poll a flag variable. However, given the weak memory model, how do we know if any of the other data we need from the eCore(s) have been already written to the memory when the write to the flag variable becomes globally visible? Is there some kind of hardware memory barrier that can guaranty that?
At the same time, is it possible to use this method for the eCore(s) to wait for the ARM processor? An example on why we might need this is if the ARM core handles network connections and we need the eCores to wait for some data.
Thank you.
Best regards,
Chris