LVDS interconnection

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

LVDS interconnection

Postby NewstHet » Mon Oct 20, 2014 11:51 am

Hey,
I have a little trouble in gathering information about how to connect board-to-board by LVDS (GPIO).

I need to connect one parallella 7010 (24 gpio) to another parallella 7010 (24 gpio). by my understanding ,it will leave me with 12 signals.

I'm new to LVDS so I have a noob questions:

1. What is the Bandwidth of that connection?
2. Do I just connect the GPIO pines by pure LVDS cable or do I need to use some kind of LVDS serializer/deserializer ?

As I said I'm new to LVDS, when using single ended I know what to do with the input/output signal. differential gets it's input by GPIOx_N_P.
3. How do I read/write the values while programming the parallella FPGA/Board.

Thanks!
NewstHet
 
Posts: 2
Joined: Mon Oct 20, 2014 11:31 am

Re: LVDS interconnection

Postby FHuettig » Mon Oct 20, 2014 6:42 pm

Greetings, and welcome to the forum!

LVDS (Low-voltage differential signaling) is just a way of moving ones and zeros between two devices, the only difference between LVDS and the single-ended signaling you already know about is that instead of one wire that has either a high level (above some threshold) or a low level (below some different threshold) you use two wires and the information is carried by the difference in voltages between the two wires. While this has the disadvantage of requiring two wires for every signal, it has great advantages in terms of speed, power, and both emitted noise and noise immunity.

Another difference is that LVDS requires a termination resistor at the receiver, while with low-speed single-ended signaling you often get away without one. With FPGAs like the Zynq this termination can be done on-chip.

But conceptually you are still just setting a high or low value at one end of the channel and conveying that information to the receiver. Because LVDS can be a lot faster than single-ended sometimes it makes sense to serialize low-speed parallel data into a higher-speed differential channel, but that decision is up to you the designer. This serialization and deserialization can also be done inside the FPGA, with some specialized blocks capable of doing this at several gigabits per second (the Zynqs used on Parallella don't have those, though).

Please note that using the standard FPGA configuration with the Parallella the GPIOs are all single-ended! You can generate a different bitstream with LVDS GPIOs from the standard sources by changing some `define's in the file "version.v":

Code: Select all
// Define included features
//`define FEATURE_HDMI  1
`define FEATURE_GPIO_EMIO  1
//`define FEATURE_GPIO_DIFF  1  <-- un-comment this
`define FEATURE_CCLK_DIV 1

// Set IOSTANDARD for GPIO pins
`define IOSTD_GPIO       "LVCMOS25"  <-- comment this
//`define IOSTD_GPIO       "LVDS_25" <-- un-comment this


That should change the GPIO block settings so it generates half the number of differential GPIOs compared to the original code, i.e. 12 IO pairs for the 7010. For completeness you should also change the VERSION_VALUE to something that won't be confused with the standard release in case some piece of software relies on that value for something.

NewstHet wrote:1. What is the Bandwidth of that connection?

The LVDS IOs on the Zynq we use can go up to one gigabit per second, for each pair, but doing that requires using the serializer/deserializer inside the FPGA. That part is relatively easy if you are comfortable with HDL design for FPGAs. How fast you can actually go depends on signal integrity concerns between the FPGAs: the connectors, the cable, and the routing on the PCBs.

NewstHet wrote:2. Do I just connect the GPIO pines by pure LVDS cable or do I need to use some kind of LVDS serializer/deserializer ?

That's up to you, and what you want to do. Basically any cable can carry LVDS signals, but some will be better than others. The reason to use a serdes would be to cut down on the number of wires you have between the two boards, but then the cable has to be much better quality (i.e. coax). Depending on your application a larger number of cheap wires (e.g. ribbon cable) can be cheaper and easier than doing the multi-gigabit serializer thing. Twisted-pair ribbon cable can work well for an LVDS bus.

NewstHet wrote:3. How do I read/write the values while programming the parallella FPGA/Board.

With the standard FPGA configuration and device tree they are connected to a linux gpio driver. It's slow, but you can experiment with the GPIOs using scripts and library code I've posted to the utils repository. If you want to do something more sophisticated you'll have to get into the FPGA code, again it depends on what you need. At the high end, using a DMA could push a gigabyte per second through the GPIOs.

Cheers
-- Fred -- Hardware Guy --
FHuettig
 
Posts: 142
Joined: Wed Jan 29, 2014 8:30 pm
Location: Lexington, MA, USA

Re: LVDS interconnection

Postby NewstHet » Mon Oct 20, 2014 8:37 pm

Thank You very much!

you gave me a good direction to follow and work on some theory.
NewstHet
 
Posts: 2
Joined: Mon Oct 20, 2014 11:31 am

Re: LVDS interconnection

Postby voyager » Sat Sep 19, 2015 10:15 pm

Hi FHuettin!
FHuettig wrote:Greetings, and welcome to the forum!
...

I want to do something like this and transfer gigabit per second data into the fpga and do some dsp math by using linux on it! if I read data from lvds pins now then how to send or read data from zynq soc in linux or how to use dma to manipulate this bunch of data in linux? do you have any doc or link that help me to do this?
voyager
 
Posts: 8
Joined: Wed Sep 16, 2015 8:01 pm


Return to Epiphany and Parallella Q & A

Who is online

Users browsing this forum: No registered users and 9 guests