Parallella Memory

[timpart]

[aolofsson]

Sorry for the confusion!! I edited the original comment to try to clarify. The original example applies only to DMA. "LDR instructions" are blocking. Still, the example below is a real problem.

[edit: New example]
A more likely scenario is the following:
0.) CoreA writes aa to addr X
....a lot of other stuff happens
1.) CoreA writes bb to addr X
2.) CoreA reads from addr X

Lesson, don't set some kind of program status/sync flag outside of local memory, without doing an explicit path flush as described here:
viewtopic.php?f=49&t=984

[greytery]

Here is :

Cheers,