E_REG_CORE_RESET

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

E_REG_CORE_RESET

Postby ralisi » Sun Nov 30, 2014 2:54 pm

I have some questions regarding the RESETCORE-register. I wrote the following function to let one core reset another core:
Code: Select all
void reset(unsigned row, unsigned col) {
    unsigned *addr;
    addr = (unsigned *) e_get_global_address(row, col, (void *) E_REG_CORE_RESET);
    *addr = 1;
    *addr = 0;
    e_irq_set(row,col,E_SYNC);
}


  • Is there a minimum time reset must be held so that everything is properly reset or are two consecutive writes, as above, okay?
  • What is the interrupt mask after the core was reset? Are other interrupts, apart from the sync interrupt, also permitted?


best regards
Raphael
ralisi
 
Posts: 15
Joined: Fri Apr 11, 2014 12:00 pm

Re: E_REG_CORE_RESET

Postby aolofsson » Sun Nov 30, 2014 4:37 pm

ralisi wrote:[*]Is there a minimum time reset must be held so that everything is properly reset or are two consecutive writes, as above, okay?

No minimum reset time, consecutive writes are ok.
ralisi wrote:[*]What is the interrupt mask after the core was reset? Are other interrupts, apart from the sync interrupt, also permitted?

After reset, all registers return to their default values (if there were any). The default is to have all interrupts enabled after reset.

Andreas
User avatar
aolofsson
 
Posts: 1005
Joined: Tue Dec 11, 2012 6:59 pm
Location: Lexington, Massachusetts,USA

Re: E_REG_CORE_RESET

Postby ralisi » Sun Nov 30, 2014 5:06 pm

Thank you for your answer.

So I will need to protect
Code: Select all
*addr = 0;
e_irq_set(row,col,E_SYNC);

against other interrupt sources.

Is there a specific reason to allow all interrupts after reset and not only the reset interrupt?

Best regards
Raphael
ralisi
 
Posts: 15
Joined: Fri Apr 11, 2014 12:00 pm


Return to Epiphany and Parallella Q & A

Who is online

Users browsing this forum: No registered users and 2 guests

cron