Questions about the Epiphany ISA

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Questions about the Epiphany ISA

Postby snim2 » Mon Jun 01, 2015 10:21 pm

Couple of quick questions. Firstly, Page 155 of the Epiphany Architecture Reference shows an Epiphany instruction decode table. Is there a plain text version of that table anywhere?

Secondly, some instructions are 16 bits wide and some are 32. Is there an easy way for the decoder to know whether a given instruction takes up 16 or 32 bits? I couldn't see an obvious pattern...

Thanks,

Sarah
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Re: Questions about the Epiphany ISA

Postby piotr5 » Wed Jun 03, 2015 10:30 am

have you looked at the sourcecode of e-run?
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Re: Questions about the Epiphany ISA

Postby snim2 » Wed Jun 03, 2015 10:38 am

Good question. I'm a little confused by this because that simulator doesn't seem to have its own repository. Have I missed something obvious there?
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Re: Questions about the Epiphany ISA

Postby aolofsson » Wed Jun 03, 2015 4:24 pm

All non trivial instructions available as 16 and 32 versions...depends on immediate siE and registers used.

Information contained in bits 3:0

Sorry, no plain text table handy.
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Re: Questions about the Epiphany ISA

Postby snim2 » Wed Jun 03, 2015 9:45 pm

Many thanks. We have found some (minor) typos in the decode table; what is the best way of reporting those? Would one of the issue trackers on GitHub be suitable?
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