GPIO, max ratings, LVDS pin pairs, and reads/writes

[ArunD]

Hello...

The Parallella manual mentions that the GPIO pins are per LVDS standard. In a way some H/W newbie questions:
1) Are these pins high input voltage and high output current protected?
2) What are the upper and lower voltage for the logic levels? What are the max ratings for analog IO?
3) Is the output to these pins also in pairs? Is it the same for analog IO?
4) The Zynq 7000 manual seems to refer to single pins, and there isn't much reference to LVDS. So is the Parallella board translating single pin voltages to LVDS?
5) Many signals I can think of working with are not differential, so are there any devices/ICs that do this readily? Same question but for the output.
6) Does the software need to read each pin pair and determine the difference? Or only one logic level is presented?

Am I missing the correct manual to refer to for these questions?

[tnt]

The IO are definitely not very protected and abusing them will damage them. There isn't much choice here, to be able to push 1 Gbits per pin you can't add protection devices, it would slow down the pins too much.

The pins on the FPGA are programmable which mean you can select which IO standard you want them to use by reprogramming the FPGA. They _can_ support LVDS25 but you don't have to use it. You can configure them to act as LVCMOS25 single ended. Snce the IO bank voltage is even programmable, you could even configure it as LVCMOS33.

All the DC and electrical specs are in :
http://www.xilinx.com/support/documenta ... -Sheet.pdf

[ArunD]

[tnt]

Changing the IO standard in the FPGA config and rebuilding it is the first step.

You also need to reprogram the PMIC on the board to output 3.3v on that power rail isntead of 2.5v, I have no idea if anyone has ever done that or how to do it in practice, I just know the HW can do it. (Be careful with that since controlling the voltage bus you could by mistake configure it for a voltage too high and physically damage the board !)

[aolofsson]

Yes, it has been done by patc I believe...

Also by Fred in this script

https://github.com/parallella/parallell ... management

[ArunD]

Thanks to you both for your responses!

My interest is in playing with the GPIO pins with single sided voltages. Is it sufficient to change "parallella_gpio_emio.v" IOBUFDS IOSTANDARD to use "LVCMOS_25" (instead of LVSMOS_33), and build the "parallella.bit.bin"? It's a learning & exploring phase, and would like to take smaller low/no risk steps.