Parallella Community

Has anyone done benchmark from core to/from external DRAM ?

I thought I had seen some a few months ago but can't find them ...

Cheers,

Sylvain

Thanks, that's consistent with what I get ( 87 Mo/s read , 234 Mo/s write ).

But that's pretty low, the interface peak is supposed to be like 900 Mo/s right ?

Please note that the host transfer speeds were measured using memcpy() calls (which is the implementation of the e_read() and e_write() API's). You can probably get better performance using DMA.

Yes.

Hmm... Host <-> ERAM bandwidth is strangely slow.

What is the Zynq's DDR configuration (operating frequency, DRAM bus width) ?

I added a section to the test, measuring the memcpy() speed withing application space (virtual memory). It happens that memcpy() between buffers within the host application (i.e., virtual to virtual space, insode the O/S DRAM segment) achieve speeds of 240 MBps.

This is about 2x the speed of DRAM to/from ERAM (reminder: ERAM here is the segment of the board's DRAM dedicated to the Epiphany and not seen by linux). I am open to explanations on *why* the two operations are so different in speeds.

Looking at the memcpy() disassembly code, it looks like the copy is done via reg read/write and not DMA.

Regarding the ZedBoard's spec - according to Roman, the default ZedBoard configuration is 533MHz Operating Frequency, 32bit effective DRAM bus width, which means ~2 GBps. However, we will look further on the documentation to see if the actual settings we have is different.

Is this understanding about eLink correct?

eLink packet size is always 104 bits.
(data:32, src_address:32, dst_address:32, control:8)

Writing 32 bits costs 104 bps of bandwidth.

Reading 32 bits costs 208 bps of bandwidth.
(104 bits for request, 104 bits for response)